View R5F6417APFB_3549814.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 1 of 109 r32c/117 group renesas mcu rej03b0254-0101 rev.1.01 mar 11, 2010 r32c/117 group datasheet 1. overview 1.1 features the m16c family offers a robust platform of 32-/16- bit cisc microcomputers (m cus) featuring high rom code efficiency, extensive emi/ems noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. extensive device scalability from low- to high-end, featuring a single architecture as well as compatib le pin assignments and peripheral functions, provides support for a vast range of application fields. the r32c/100 series is a high-end microcontroller series in the m16c family. with a 4-gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit cisc architecture, multiplier, multiply-accumulate unit, and floating point unit. the selection from the broadest choice of on- chip peripheral devices ? uart, crc, dm ac, a/d and d/a converters, timers, i 2 c, and wdt enables to minimize external components. the r32c/100 series, in particular, provides the r32c/117 group as a standard product. this product, provided as a 100/144-pin plastic molded lqfp package, configures nine channels of serial interface, one channel of multi-master i 2 c-bus interface, and one channel of can module. 1.1.1 applications car audio, audio, printer, office/industrial equipment etc.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 2 of 109 r32c/117 group 1. overview 1.1.2 performance overview table 1.1 to table 1.4 show the performance overview of the r32c/117 group. note: 1. please contact a renesas sales office to use the optional feature. table 1.1 r32c/117 group performance for the 144 pin-package (1/2) unit function performance cpu central processing unit r32c/100 series cpu core ? basic instructions: 108 ? minimum instruction execution time: 20 ns (f(cpu) = 50 mhz) ? multiplier: 32-bit 32-bit 64-bit ? multiply-accumulate unit: 32-bit 32-bit + 64-bit 64-bit ? ieee-754 floating point st andard: single precision ? 32-bit barrel shifter ? operating mode: single-chip mode, memory expansion mode, microprocessor mode (optional (1) ) memory flash memory: 384 kbytes to 1 mbyte ram: 40 k/48 k/63 kbytes data flash: 4 kbytes 2 blocks refer to table 1.5 for memory size of each product group voltage detector low voltage detector optional (1) low voltage detection interrupt clock clock generator ? 4 circuits (main clo ck, sub clock, pll, on-chip oscillator) ? oscillation stop detector: main clock oscillator stop/re-oscillation detection ? frequency divide circuit: divide-by-2 to divide-by-24 selectable ? low power modes: wait mode, stop mode external bus expansion bus and memory expansion ? address space: 4 gbytes (of which up to 64 mbytes is user accessible) ? external bus interface: support for wa it-state insertion, 4 chip select outputs ? bus format: separate bus/multiplexed bus sele ctable, data bus width selectable (8/16/32 bits) interrupts interrupt vectors: 261 external interrupt inputs: nmi , int 9, key input 4 interrupt priority levels: 7 levels watchdog timer 15 bits 1 (selectable input frequency from prescaler output) dma dmac 4 channels ? cycle-steal transfer mode ? request sources: 57 ? 2 transfer modes: single transfer, repeat transfer dmac ii ? can be activated by any peripheral interrupt source ? 3 transfer functions: immediate da ta transfer, calculation transfer, chained transfer i/o ports programmable i/o ports ? 2 input-only ports ? 120 cmos inputs/outputs ? 32 ports are 5 v tolerant ? a pull-up resistor is selectable for every 4 input ports (except 5 v tolerant inputs)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 3 of 109 r32c/117 group 1. overview notes: 1. iebus is a trademark of nec electronics corporation. 2. please contact a renesas sales office to use the optional feature. table 1.2 r32c/117 group performance for the 144-pin package (2/2) unit function performance timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse-width modulation (pwm) mode two-phase pulse signal processing in event counter mode (two- phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode three-phase motor control timer three-phase motor control timer 1 (timers a1, a2, a4, and b2 used) 8-bit programmable dead time timer serial interface uart0 to uart8 asynchronous/synchronous serial interface 9 channels ?i 2 c-bus (uart0 to uart6) ? special mode 2 (uart0 to uart6) ? iebus (1) (optional (2) ) (uart0 to uart6) a/d converter 10-bit resolution 34 channels sample and hold functionality integrated d/a converter 8-bit resolution 2 crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1) x-y converter 16 bits 16 bits intelligent i/o time measurement (input capture): 16 bits 16 waveform generation (output compare): 16 bits 24 serial interface: variable-length synchronous serial i/o mode, iebus (1) mode (optional (2) ) multi-master i 2 c-bus interface 1 channel can module 1 channel can functionality compliant with iso11898-1 32 mailboxes flash memory programming and erasure s upply voltage: vcc = 3.0 to 5.5 v minimum endurance: 1,000 program/erase cycles security protection: rom code protect, id code protect debugging: on-chip debug, on-board flash programming operating frequency/supply voltage 50 mhz/vcc = 3.0 to 5.5 v operating temperature -20c to 85c (version n) -40c to 85c (version d) -40c to 85c (version p) current consumption 35 ma (vcc = 5.0 v, f(cpu) = 50 mhz) 8 a (vcc = 3.3 v, f(xcin) = 32.768 khz, in wait mode) package 144-pin plastic molded lqfp (plqp0144ka-a)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 4 of 109 r32c/117 group 1. overview note: 1. please contact a renesas sales office to use the optional feature. table 1.3 r32c/117 group performance for the 100-pin package (1/2) unit function performance cpu central processing unit r32c/100 series cpu core ? basic instructions: 108 ? minimum instruction execution time: 20 ns (f(cpu) = 50 mhz) ? multiplier: 32-bit 32-bit 64-bit ? multiply-accumulate unit: 32-bit 32-bit + 64-bit 64-bit ? ieee-754 floating point st andard: single precision ? 32-bit barrel shifter ? operating mode: single-chip mode, memory expansion mode, microprocessor mode (optional (1) ) memory flash memory: 128 kbytes to 1 mbyte ram: 20 k/40 k/48 k/63 kbytes data flash: 4 kbytes 2 blocks refer to table 1.5 for memory size of each product group voltage detector low voltage detector optional (1) low voltage detection interrupt clock clock generator ? 4 circuits (main clo ck, sub clock, pll, on-chip oscillator) ? oscillation stop detector: main clock oscillator stop/re-oscillation detection ? frequency divide circuit: divide-by-2 to divide-by-24 selectable ? low power modes: wait mode, stop mode external bus expansion bus and memory expansion ? address space: 4 gbytes (of which up to 64 mbytes is user accessible) ? external bus interface: support for wa it-state insertion, 4 chip select outputs ? bus format: separate bus/multiplexed bus sele ctable, data bus width selectable (8/16 bits) interrupts interrupt vectors: 261 external interrupt inputs: nmi , int 6, key input 4 interrupt priority levels: 7 levels watchdog timer 15 bits 1 (selectable input frequency from prescaler output) dma dmac 4 channels ? cycle-steal transfer mode ? request sources: 51 ? 2 transfer modes: single transfer, repeat transfer dmac ii ? can be activated by any peripheral interrupt source ? 3 transfer functions: immediate da ta transfer, calculation transfer, chained transfer i/o ports programmable i/o ports ? 2 input-only ports ? 84 cmos inputs/outputs ? 32 ports are 5 v tolerant ? a pull-up resistor is selectable for every 4 input ports (except 5 v tolerant inputs)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 5 of 109 r32c/117 group 1. overview notes: 1. iebus is a trademark of nec electronics corporation. 2. please contact a renesas sales office to use the optional feature. table 1.4 r32c/117 group performance for the 100-pin package (2/2) unit function performance timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse-width modulation (pwm) mode two-phase pulse signal processing in event counter mode (two- phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode three-phase motor control timer three-phase motor control timer 1 (timers a1, a2, a4, and b2 used) 8-bit programmable dead time timer serial interface uart0 to uart8 asynchronous/synchronous serial interface 9 channels ?i 2 c-bus (uart0 to uart6) ? special mode 2 (uart0 to uart6) ? iebus (1) (optional (2) ) (uart0 to uart6) a/d converter 10-bit resolution 26 channels sample and hold functionality integrated d/a converter 8-bit resolution 2 crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1) x-y converter 16 bits 16 bits intelligent i/o time measurement (input capture): 16 bits 16 waveform generation (output compare): 16 bits 19 serial interface: variable-length synchronous serial i/o mode, iebus (1) mode (optional (2) ) multi-master i 2 c-bus interface 1 channel can module 1 channel can functionality compliant with iso11898-1 32 mailboxes flash memory programming and erasure s upply voltage: vcc = 3.0 to 5.5 v minimum endurance: 1,000 program/erase cycles security protection: rom code protect, id code protect debugging: on-chip debug, on-board flash programming operating frequency/supply voltage 50 mhz/vcc = 3.0 to 5.5 v operating temperature -20c to 85c (version n) -40c to 85c (version d) -40c to 85c (version p) current consumption 35 ma (vcc = 5.0 v, f(cpu) = 50 mhz) 8 a (vcc = 3.3 v, f(xcin) = 32.768 khz, in wait mode) package 100-pin plastic molded lqfp (plqp0100kb-a)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 6 of 109 r32c/117 group 1. overview 1.2 product information table 1.5 and table 1.6 list the product information an d figure 1.1 shows the details of the part number. notes: 1. the old package codes are as follows:plqp0 100kb-a: 100p6q-a, plqp0144ka-a: 144p6q-a 2. data flash memory provides an add itional 8 kbytes of rom capacity. table 1.5 r32c/117 group product list (1/2) as of march, 2010 part number package code (1) rom capacity (2) ram capacity remarks r5f6417bnfb (p) plqp0100kb-a 128 kbytes + 8 kbytes 20 kbytes -20c to 85c (version n) r5f6417bdfb (d) -40c to 85c (version d) r5f6417bpfb (p) -40c to 85c (version p) r5f6417anfb (p) plqp0100kb-a 256 kbytes + 8 kbytes -20c to 85c (version n) r5f6417adfb -40c to 85c (version d) R5F6417APFB (p) -40c to 85c (version p) r5f64175nfd (p) plqp0144ka-a 384 kbytes + 8 kbytes 40 kbytes -20c to 85c (version n) r5f64175dfd -40c to 85c (version d) r5f64175pfd -40c to 85c (version p) r5f64175nfb (p) plqp0100kb-a -20c to 85c (version n) r5f64175dfb -40c to 85c (version d) r5f64175pfb -40c to 85c (version p) r5f64176nfd (p) plqp0144ka-a 512 kbytes + 8 kbytes -20c to 85c (version n) r5f64176dfd -40c to 85c (version d) r5f64176pfd -40c to 85c (version p) r5f64176nfb (p) plqp0100kb-a -20c to 85c (version n) r5f64176dfb -40c to 85c (version d) r5f64176pfb -40c to 85c (version p) r5f64177nfd (p) plqp0144ka-a 640 kbytes + 8 kbytes 48 kbytes -20c to 85c (version n) r5f64177dfd -40c to 85c (version d) r5f64177pfd -40c to 85c (version p) r5f64177nfb (p) plqp0100kb-a -20c to 85c (version n) r5f64177dfb -40c to 85c (version d) r5f64177pfb -40c to 85c (version p) (d): under development (p): on planning phase
rej03b0254-0101 rev.1.01 mar 11, 2010 page 7 of 109 r32c/117 group 1. overview notes: 1. the old package codes are as follows:plqp0 100kb-a: 100p6q-a, plqp0144ka-a: 144p6q-a 2. data flash memory provides an add itional 8 kbytes of rom capacity. table 1.6 r32c/117 group product list (2/2) as of march, 2010 part number package code (1) rom capacity (2) ram capacity remarks r5f64178nfd (p) plqp0144ka-a 768 kbytes + 8 kbytes 63 kbytes -20c to 85c (version n) r5f64178dfd -40c to 85c (version d) r5f64178pfd -40c to 85c (version p) r5f64178nfb (p) plqp0100kb-a -20c to 85c (version n) r5f64178dfb -40c to 85c (version d) r5f64178pfb -40c to 85c (version p) r5f64179nfd (p) plqp0144ka-a 1 mbyte + 8 kbytes -20c to 85c (version n) r5f64179dfd -40c to 85c (version d) r5f64179pfd -40c to 85c (version p) r5f64179nfb (p) plqp0100kb-a -20c to 85c (version n) r5f64179dfb -40c to 85c (version d) r5f64179pfb -40c to 85c (version p) (d): under development (p): on planning phase
rej03b0254-0101 rev.1.01 mar 11, 2010 page 8 of 109 r32c/117 group 1. overview figure 1.1 part numbering part number r5 f 64 17 9 p xxx fd package code fb : plqp0100kb-a fd : plqp0144ka-a rom number omitted in the flash memory version rom/ram capacity b : 128 kb/20 kb a : 256 kb/20 kb 5 : 384 kb/40 kb 6 : 512 kb/40 kb 7 : 640 kb/48 kb 8 : 768 kb/63 kb 9:1 mb/63 kb temperature code n : -20c to 85c d : -40c to 85c p : -40c to 85c memory type f : flash memory version r32c/117 group r32c/100 series
rej03b0254-0101 rev.1.01 mar 11, 2010 page 9 of 109 r32c/117 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram of the r32c/117 group. figure 1.2 r32c/117 group block diagram port p0 port p1 port p2 port p3 port p4 port p5 port p6 8 8 8 8 8 8 8 port p7 p8_5 port p9 port p10 8 7 8 (3) 8 peripheral functions timer: timer a 16 bits 5 timers timer b 16 bits 6 timers three-phase motor controller watchdog timer: 15 bits d/a converter: 8 bits 2 channels a/d converter: 10 bits 1 circuit standard: 10 inputs maximum: 34 inputs (1) serial interface: 9 channels x-y converter: 16 bits 16 bits clock generator: 4 circuits - xin-xout - xcin-xcout - on-chip oscillator - pll frequency synthesizer dmac crc calculator (ccitt) x 16 + x 12 + x 5 + 1 intelligent i/o time measurement: 16 wave generation: 24 (2) serial interface: - variable-length synchronous serial i/o - iebus (4) r32c/100 series cpu core r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb flg intb isp usp pc svf svp vct r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb memory rom ram multiplier port p14 port p14_1 port p11 port p12 port p13 4 5 8 8 dmac ii floating-point unit port p8 port p15 8 (note 5) notes: 1. 34 inputs are available in the 144-pin package. in the 100-pin package, up to 26 inputs are provided. 2. 24 outputs are available in the 144-pin package . in the 100-pin package, 19 outputs are provided. 3. eight ports are available in the 144-pin package. in the 100-pin package, five i/o ports and one input- only port (p9_1) are provided. 4. iebus is a trademark of nec electronics corporation. 5. ports p11 to p15 are available in the 144-pin package only. multi-master i 2 c-bus interface: 1 channel can module: 1 channel
rej03b0254-0101 rev.1.01 mar 11, 2010 page 10 of 109 r32c/117 group 1. overview 1.4 pin assignments figure 1.3 and figure 1.4 show the pin assignments (t op view) and table 1.7 to table 1.13 show the pin characteristics. figure 1.3 pin assignment for the 144-pin package (top view) notes: 1. pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins. 2. the following pins are 5 v tolerant inputs: p4_0 to p4_7, p5_4 to p5_7, p6_0 to p6_7, p7_0 to p7_7, and p8_0 to p8_3 3. the position of pin number 1 varies by product. refer to the index mark in attached ?package dimensions?. 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82 81 80 79 78 77 76 75 74 88 73 stxd4 / scl4 / rxd4 / adtrg / p9_7 p7_0 / ta0out / txd2 / sda2 / srxd2 / iio1_6 / outc2_0 / istxd2 / ieout / msda p6_7 / txd1 / sda1 / srxd1 avcc vref an_0 / p10_0 avss an_1 / p10_1 an_2 / p10_2 an_3 / p10_3 ki0 / an_4 / p10_4 ki1 / an_5 / p10_5 ki2 / an_6 / p10_6 ki3 / an_7 / p10_7 vcc iio0_0 / txd7 / an15_0 / p15_0 vss iio0_1 / clk7 / an15_1 / p15_1 iio0_2 / rxd7 / an15_2 / p15_2 iio0_3 / rts7 / cts7 / an15_3 / p15_3 iio0_4 / txd6 / sda6 / srxd6 / an15_4 / p15_4 iio0_5 / rxd6 / scl6 / stxd6 / an15_5 / p15_5 iio0_6 / clk6 / an15_6 / p15_6 iio0_7 / rts6 / cts6 / ss6 / an15_7 / p15_7 an0_0 / d0 / p0_0 an0_1 / d1 / p0_1 an0_2 / d2 / p0_2 an0_3 / d3 / p0_3 iio1_0 / txd8 / cs0 / p11_0 iio1_1 / clk8 / cs1 / p11_1 iio1_2 / rxd8 / cs2 / p11_2 iio1_3 / rts8 / cts8 / wr2 / cs3 / p11_3 wr3 / bc3 / p11_4 an0_4 / d4 / p0_4 an0_5 / d5 / p0_5 an0_6 / d6 / p0_6 an0_7 / d7 / p0_7 iio0_0 / iio1_0 / d8 / p1_0 vcc p6_6 / rxd1 / scl1 / stxd1 vss p6_5 / clk1 p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 p6_3 / txd0 / sda0 / srxd0 p6_2 / tb2in / rxd0 / scl0 / stxd0 p6_1 / tb1in / clk0 p6_0 / tb0in / cts0 / rts0 / ss0 p13_7 / d31 / outc2_7 p13_6 / d30 / outc2_1 / isclk2 p13_5 / d29 / outc2_2 / isrxd2 / iein p13_4 / d28 / outc2_0 / istxd2 / ieout p5_7 / rdy / cs3 / cts7 / rts7 p5_6 / ale / cs2 / rxd7 p5_5 / hold / clk7 p5_4 / hlda / cs1 / txd7 p13_3 / d27 / outc2_3 vss p13_2 / d26 / outc2_6 vcc p13_1 / d25 / outc2_5 p13_0 / d24 / outc2_4 p5_3 / clkout / bclk p5_2 / rd p5_1 / wr1 / bc1 p5_0 / wr0 / wr p12_7 / d23 p12_6 / d22 p12_5 / d21 p4_7 / cs0 / a23 / txd6 / sda6 / srxd6 p4_6 / cs1 / a22 / rxd6 / scl6 / stxd6 p4_5 / cs2 / a21 / clk6 p4_4 / cs3 / a20 / cts6 / rts6 / ss6 srxd4 / sda4 / txd4 / anex1 / p9_6 clk4 / anex0 / p9_5 ss4 / rts4 / cts4 / tb4in / da1 / p9_4 ieout / istxd2 / outc2_0 / srxd3 / sda3 / txd3 / tb2in / p9_2 iein / isrxd2 / stxd3 / scl3 / rxd3 / tb1in / p9_1 clk3 / tb0in / p9_0 int8 / p14_6 int7 / p14_5 int6 / p14_4 p14_3 nsd cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc nmi / p8_5 int2 / p8_4 can0in / can0wu / int1 / p8_3 can0out / int0 / p8_2 ud0b / ud1b / iio1_5 / rts5 / cts5 / ss5 / u / ta4in / p8_1 ud0a / ud1a / rxd5 / scl5 / stxd5 / u / ta4out / p8_0 can0in / can0wu / ud0b / ud1b / iio1_4 / clk5 / ta3in / p7_7 can0out / ud0a / ud1a / iio1_3 / rts8 / cts8 / txd5 / sda5 / srxd5 / ta3out / p7_6 iio1_2 / rxd8 / w / ta2in / p7_5 iio1_1 / clk8 / w / ta2out / p7_4 iio1_0 / txd8 / ss2 / rts2 / cts2 / v / ta1in / p7_3 clk2 / v / ta1out / p7_2 mscl / iein / isrxd2 / outc2_2 / iio1_7 / stxd2 / scl2 / rxd2 / ta0in / tb5in / p7_1 ss3 / rts3 / cts3 / tb3in / da0 / p9_3 vdc0 p14_1 vdc1 p1_1 / d9 / iio0_1 / iio1_1 p1_2 / d10 / iio0_2 / iio1_2 p1_3 / d11 / iio0_3 / iio1_3 p1_4 / d12 / iio0_4 / iio1_4 p1_5 / d13 / int3 / iio0_5 / iio1_5 p1_6 / d14 / int4 / iio0_6 / iio1_6 p1_7 / d15 / int5 / iio0_7 / iio1_7 p2_0 / a0 / [a0/d0] / bc0 / [bc0/d0] / an2_0 vss p3_0 / a8 / [a8/d8] / ta0out / ud0a / ud1a vcc p12_0 / d16 / txd6 / sda6 / srxd6 p12_1 / d17 / clk6 p12_2 / d18 / rxd6 / scl6 / stxd6 p12_3 / d19 / cts6 / rts6 / ss6 p12_4 / d20 p3_1 / a9 / [a9/d9] / ta3out / ud0b / ud1b p3_2 / a10 / [a10/d10] / ta1out / v p3_3 / a11 / [a11/d11] / ta1in / v p3_4 / a12 / [a12/d12] / ta2out / w p3_5 / a13 / [a13/d13] / ta2in / w p3_6 / a14 / [a14/d14] / ta4out / u p3_7 / a15 / [a15/d15] / ta4in / u p4_0 / a16 / cts3 / rts3 / ss3 p4_1 / a17 / clk3 vss p4_2 / a18 / rxd3 / scl3 / stxd3 / isrxd2 / iein vcc p4_3 / a19 / txd3 / sda3 / srxd3 / outc2_0 / istxd2 / ieout p2_1 / a1 / [a1/d1] / bc2 / [bc2/d1] / an2_1 p2_2 / a2 / [a2/d2] / an2_2 p2_3 / a3 / [a3/d3] / an2_3 p2_4 / a4 / [a4/d4] / an2_4 p2_5 / a5 / [a5/d5] / an2_5 p2_6 / a6 / [a6/d6] / an2_6 p2_7 / a7 / [a7/d7] / an2_7 plqp0144ka-a (144p6q-a) (top view) r32c/117 group (note 3) (note 1) (note 2)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 11 of 109 r32c/117 group 1. overview table 1.7 pin characteristics for the 144-pin package (1/4) pin no. control pin port interrupt pin timer pin uart/can module pin intelligent i/o pin analog pin bus control pin 1 p9_6 txd4/sda4/srxd4 anex1 2 p9_5 clk4 anex0 3p9_4tb4in cts4 / rts4 / ss4 da1 4p9_3tb3in cts3 / rts3 / ss3 da0 5 p9_2 tb2in txd3/sda3/srxd3 outc2_0/istxd2/ ieout 6 p9_1 tb1in rxd3/scl3/stxd3 isrxd2/iein 7 p9_0 tb0in clk3 8 p14_6 int8 9 p14_5 int7 10 p14_4 i nt6 11 p14_3 12 vdc0 13 p14_1 14 vdc1 15 nsd 16 cnvss 17 xcin p8_7 18 xcout p8_6 19 reset 20 xout 21 vss 22 xin 23 vcc 24 p8_5 nmi 25 p8_4 int2 26 p8_3 int1 can0in/ can0wu 27 p8_2 int0 can0out 28 p8_1 ta4in/ ucts5 / rts5 / ss5 iio1_5/ud0b/ud1b 29 p8_0 ta4out/u rxd5/scl5/stxd5 ud0a/ud1a 30 p7_7 ta3in clk5/can0in/ can0wu iio1_4/ud0b/ud1b 31 p7_6 ta3out txd5/sda5/srxd5/ cts8 / rts8 /can0out iio1_3/ud0a/ud1a 32 p7_5 ta2in/ w rxd8 iio1_2 33 p7_4 ta2out/w clk8 iio1_1 34 p7_3 ta1in/ vcts2 / rts2 / ss2 /txd8 iio1_0 35 p7_2 ta1out/v clk2 36 p7_1 tb5in/ ta0in rxd2/scl2/stxd2/ mscl iio1_7/outc2_2/ isrxd2/iein
rej03b0254-0101 rev.1.01 mar 11, 2010 page 12 of 109 r32c/117 group 1. overview table 1.8 pin characteristics for the 144-pin package (2/4) pin no. control pin port interrupt pin timer pin uart/can module pin intelligent i/o pin analog pin bus control pin 37 p7_0 ta0out txd2/sda2/srxd2/ msda iio1_6/outc2_0/ istxd2/ieout 38 p6_7 txd1/sda1/srxd1 39 vcc 40 p6_6 rxd1/scl1/stxd1 41 vss 42 p6_5 clk1 43 p6_4 cts1 / rts1 / ss1 outc2_1/isclk2 44 p6_3 txd0/sda0/srxd0 45 p6_2 tb2in rxd0/scl0/stxd0 46 p6_1 tb1in clk0 47 p6_0 tb0in cts0 / rts0 / ss0 48 p13_7 outc2_7 d31 49 p13_6 outc2_1/isclk2 d30 50 p13_5 outc2_2/isrxd2/ iein d29 51 p13_4 outc2_0/istxd2/ ieout d28 52 p5_7 cts7 / rts7 rdy/cs3 53 p5_6 rxd7 ale/ cs2 54 p5_5 clk7 hold 55 p5_4 txd7 hlda / cs1 56 p13_3 outc2_3 d27 57 vss 58 p13_2 outc2_6 d26 59 vcc 60 p13_1 outc2_5 d25 61 p13_0 outc2_4 d24 62 p5_3 clkout/ bclk 63 p5_2 rd 64 p5_1 wr1 / bc1 65 p5_0 wr0 / wr 66 p12_7 d23 67 p12_6 d22 68 p12_5 d21 69 p4_7 txd6/sda6/srxd6 cs0 /a23 70 p4_6 rxd6/scl6/stxd6 cs1 /a22 71 p4_5 clk6 cs2 /a21 72 p4_4 cts6 / rts6 / ss6 cs3 /a20 73 p4_3 txd3/sda3/srxd3 outc2_0/istxd2/ ieout a19 74 vcc
rej03b0254-0101 rev.1.01 mar 11, 2010 page 13 of 109 r32c/117 group 1. overview table 1.9 pin characteristics for the 144-pin package (3/4) pin no. control pin port interrupt pin timer pin uart/can module pin intelligent i/o pin analog pin bus control pin 75 p4_2 rxd3/scl3/st xd3 isrxd2/iein a18 76 vss 77 p4_1 clk3 a17 78 p4_0 cts3 / rts3 / ss3 a16 79 p3_7 ta4in/ u a15(/d15) 80 p3_6 ta4out/u a14(/d14) 81 p3_5 ta2in/ w a13(/d13) 82 p3_4 ta2out/w a12(/d12) 83 p3_3 ta1in/ v a11(/d11) 84 p3_2 ta1out/v a10(/d10) 85 p3_1 ta3out ud0b/ud1b a9(/d9) 86 p12_4 d20 87 p12_3 cts6 / rts6 / ss6 d19 88 p12_2 rxd6/scl6/stxd6 d18 89 p12_1 clk6 d17 90 p12_0 txd6/sda6/srxd6 d16 91 vcc 92 p3_0 ta0out ud0a/ud1a a8(/d8) 93 vss 94 p2_7 an2_7 a7(/d7) 95 p2_6 an2_6 a6(/d6) 96 p2_5 an2_5 a5(/d5) 97 p2_4 an2_4 a4(/d4) 98 p2_3 an2_3 a3(/d3) 99 p2_2 an2_2 a2(/d2) 100 p2_1 an2_1 a1(/d1)/ bc2 (/d1) 101 p2_0 an2_0 a0(/d0)/ bc0 (/d0) 102 p1_7 int5 iio0_7/iio1_7 d15 103 p1_6 int4 iio0_6/iio1_6 d14 104 p1_5 int3 iio0_5/iio1_5 d13 105 p1_4 iio0_4/iio1_4 d12 106 p1_3 iio0_3/iio1_3 d11 107 p1_2 iio0_2/iio1_2 d10 108 p1_1 iio0_1/iio1_1 d9 109 p1_0 iio0_0/iio1_0 d8 110 p0_7 an0_7 d7 111 p0_6 an0_6 d6 112 p0_5 an0_5 d5 113 p0_4 an0_4 d4 114 p11_4 bc3 / wr3
rej03b0254-0101 rev.1.01 mar 11, 2010 page 14 of 109 r32c/117 group 1. overview table 1.10 pin characteristics for the 144-pin package (4/4) pin no. control pin port interrupt pin timer pin uart/can module pin intelligent i/o pin analog pin bus control pin 115 p11_3 cts8 / rts8 iio1_3 cs3 / wr2 116 p11_2 rxd8 iio1_2 cs2 117 p11_1 clk8 iio1_1 cs1 118 p11_0 txd8 iio1_0 cs0 119 p0_3 an0_3 d3 120 p0_2 an0_2 d2 121 p0_1 an0_1 d1 122 p0_0 an0_0 d0 123 p15_7 cts6 / rts6 / ss6 iio0_7 an15_7 124 p15_6 clk6 iio0_6 an15_6 125 p15_5 rxd6/scl6/stxd6 iio0_5 an15_5 126 p15_4 txd6/sda6/srxd6 iio0_4 an15_4 127 p15_3 cts7 / rts7 iio0_3 an15_3 128 p15_2 rxd7 iio0_2 an15_2 129 p15_1 clk7 iio0_1 an15_1 130 vss 131 p15_0 txd7 iio0_0 an15_0 132 vcc 133 p10_7 ki3 an_7 134 p10_6 ki2 an_6 135 p10_5 ki1 an_5 136 p10_4 ki0 an_4 137 p10_3 an_3 138 p10_2 an_2 139 p10_1 an_1 140 avss 141 p10_0 an_0 142 vref 143 avcc 144 p9_7 rxd4/scl4/stxd4 adtrg
rej03b0254-0101 rev.1.01 mar 11, 2010 page 15 of 109 r32c/117 group 1. overview figure 1.4 pin assignment for the 100-pin package (top view) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 100 99 98 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82 81 80 79 78 77 76 75 74 88 73 stxd4 / scl4 / rxd4 / adtrg / p9_7 p7_0 / ta0out / txd2 / sda2 / srxd2 / iio1_6 / outc2_0 / istxd2 / ieout / msda p6_7 / txd1 / sda1 / srxd1 avcc vref an_0 / p10_0 avss an_1 / p10_1 an_2 / p10_2 an_3 / p10_3 ki0 / an_4 / p10_4 ki1 / an_5 / p10_5 ki2 / an_6 / p10_6 ki3 / an_7 / p10_7 an0_0 / d0 / p0_0 an0_1 / d1 / p0_1 an0_2 / d2 / p0_2 an0_3 / d3 / p0_3 an0_4 / d4 / p0_4 an0_5 / d5 / p0_5 an0_6 / d6 / p0_6 an0_7 / d7 / p0_7 p6_6 / rxd1 / scl1 / stxd1 p6_5 / clk1 p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 p6_3 / txd0 / sda0 / srxd0 p6_2 / tb2in / rxd0 / scl0 / stxd0 p6_1 / tb1in / clk0 p6_0 / tb0in / cts0 / rts0 / ss0 p5_7 / rdy / cs3 / cts7 / rts7 p5_6 / ale / cs2 / rxd7 p5_5 / hold / clk7 p5_4 / hlda / cs1 / txd7 p5_3 / clkout / bclk p5_2 / rd p5_1 / wr1 / bc1 p5_0 / wr0 / wr p4_7 / cs0 / a23 / txd6 / sda6 / srxd6 p4_6 / cs1 / a22 / rxd6 / scl6 / stxd6 p4_5 / cs2 / a21 / clk6 p4_4 / cs3 / a20 / cts6 / rts6 / ss6 srxd4 / sda4 / txd4 / anex1 / p9_6 clk4 / anex0 / p9_5 ss4 / rts4 / cts4 / tb4in / da1 / p9_4 vdc0 p9_1 vdc1 nsd cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc nmi / p8_5 int2 / p8_4 can0in / can0wu / int1 / p8_3 can0out / int0 / p8_2 ud0b / ud1b / iio1_5 / rts5 / cts5 / ss5 / u / ta4in / p8_1 ud0a / ud1a / rxd5 / scl5 / stxd5 / u / ta4out / p8_0 can0in / can0wu / ud0b / ud1b / iio1_4 / clk5 / ta3in / p7_7 can0out / ud0a / ud1a / iio1_3 / rts8 / cts8 / txd5 / sda5 / srxd5 / ta3out / p7_6 iio1_2 / rxd8 / w / ta2in / p7_5 iio1_1 / clk8 / w / ta2out / p7_4 iio1_0 / txd8 / ss2 / rts2 / cts2 / v / ta1in / p7_3 p7_2 / ta1out / v / clk2 p7_1 / tb5in / ta0in / rxd2 / scl2 / stxd2 / iio1_7 / outc2_2 / isrxd2 / iein / mscl tb3in / da0 / p9_3 iio0_1 / iio1_1 / d9 / p1_1 iio0_2 / iio1_2 / d10 / p1_2 p1_3 / d11 / iio0_3 / iio1_3 p1_4 / d12 / iio0_4 / iio1_4 p1_5 / d13 / int3 / iio0_5 / iio1_5 p1_6 / d14 / int4 / iio0_6 / iio1_6 p1_7 / d15 / int5 / iio0_7 / iio1_7 p2_0 / a0 / [a0/d0] / bc0 / [bc0/d0] / an2_0 vss p3_0 / a8 / [a8/d8] / ta0out / ud0a / ud1a vcc p3_1 / a9 / [a9/d9] / ta3out / ud0b / ud1b p3_2 / a10 / [a10/d10] / ta1out / v p3_3 / a11 / [a11/d11] / ta1in / v p3_4 / a12 / [a12/d12] / ta2out / w p3_5 / a13 / [a13/d13] / ta2in / w p3_6 / a14 / [a14/d14] / ta4out / u p3_7 / a15 / [a15/d15] / ta4in / u p4_0 / a16 / cts3 / rts3 / ss3 p4_1 / a17 / clk3 p4_2 / a18 / rxd3 / scl3 / stxd3 / isrxd2 / iein p4_3 / a19 / txd3 / sda3 / srxd3 / outc2_0 / istxd2 / ieout p2_1 / a1 / [a1/d1] / an2_1 p2_2 / a2 / [a2/d2] / an2_2 p2_3 / a3 / [a3/d3] / an2_3 p2_4 / a4 / [a4/d4] / an2_4 p2_5 / a5 / [a5/d5] / an2_5 p2_6 / a6 / [a6/d6] / an2_6 p2_7 / a7 / [a7/d7] / an2_7 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 iio0_0 / iio1_0 / d8 / p1_0 plqp0100kb-a (100p6q-a) (top view) r32c/117 group (note 1) (note 3) (note 2) notes: 1. pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins. 2. the following pins are 5 v tolerant inputs: p4_0 to p4_7, p5_4 to p5_7, p6_0 to p6_7, p7_0 to p7_7, and p8_0 to p8_3 3. the position of pin number 1 varies by product. refer to the index mark in attached ?package dimensions?.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 16 of 109 r32c/117 group 1. overview table 1.11 pin characteristics for the 100-pin package (1/3) pin no. control pin port interrupt pin timer pin uart/can module pin intelligent i/o pin analog pin bus control pin 1p9_4tb4in cts4 / rts4 / ss4 da1 2p9_3tb3in da0 3 vdc0 4p9_1 5 vdc1 6nsd 7 cnvss 8xcinp8_7 9 xcout p8_6 10 reset 11 xout 12 vss 13 xin 14 vcc 15 p8_5 nmi 16 p8_4 int2 17 p8_3 int1 can0in/ can0wu 18 p8_2 int0 can0out 19 p8_1 ta4in/ ucts5/rts5 / ss5 iio1_5/ud0b/ud1b 20 p8_0 ta4out/u rxd5/scl5/stxd5 ud0a/ud1a 21 p7_7 ta3in clk5/can0in/ can0wu iio1_4/ud0b/ud1b 22 p7_6 ta3out txd5/sda5/srxd5/ cts8 / rts8 /can0out iio1_3/ud0a/ud1a 23 p7_5 ta2in/ w rxd8 iio1_2 24 p7_4 ta2out/w clk8 iio1_1 25 p7_3 ta1in/ vcts2 / rts2 / ss2 /txd8 iio1_0 26 p7_2 ta1out/v clk2 27 p7_1 tb5in/ ta0in rxd2/scl2/stxd2/ mscl iio1_7/outc2_2/ isrxd2/iein 28 p7_0 ta0out txd2/sda2/srxd2/ msda iio1_6/outc2_0/ istxd2/ieout 29 p6_7 txd1/sda1/srxd1 30 p6_6 rxd1/scl1/stxd1 31 p6_5 clk1 32 p6_4 cts1 / rts1 / ss1 outc2_1/isclk2 33 p6_3 txd0/sda0/srxd0 34 p6_2 tb2in rxd0/scl0/stxd0 35 p6_1 tb1in clk0 36 p6_0 tb0in cts0 / rts0 / ss0 37 p5_7 cts7 / rts7 rdy / cs3 38 p5_6 rxd7 ale/ cs2
rej03b0254-0101 rev.1.01 mar 11, 2010 page 17 of 109 r32c/117 group 1. overview table 1.12 pin characteristics for the 100-pin package (2/3) pin no. control pin port interrupt pin timer pin uart/can module pin intelligent i/o pin analog pin bus control pin 39 p5_5 clk7 hold 40 p5_4 txd7 hlda / cs1 41 p5_3 clkout/ bclk 42 p5_2 rd 43 p5_1 wr1 / bc1 44 p5_0 wr0 / wr 45 p4_7 txd6/sda6/srxd6 cs0 /a23 46 p4_6 rxd6/scl6/stxd6 cs1 /a22 47 p4_5 clk6 cs2 /a21 48 p4_4 cts6 / rts6 / ss6 cs3 /a20 49 p4_3 txd3/sda3/srxd3 outc2_0/istxd2/ ieout a19 50 p4_2 rxd3/scl3/st xd3 isrxd2/iein a18 51 p4_1 clk3 a17 52 p4_0 cts3 / rts3 / ss3 a16 53 p3_7 ta4in/ u a15(/d15) 54 p3_6 ta4out/u a14(/d14) 55 p3_5 ta2in/ w a13(/d13) 56 p3_4 ta2out/w a12(/d12) 57 p3_3 ta1in/ v a11(/d11) 58 p3_2 ta1out/v a10(/d10) 59 p3_1 ta3out ud0b/ud1b a9(/d9) 60 vcc 61 p3_0 ta0out ud0a/ud1a a8(/d8) 62 vss 63 p2_7 an2_7 a7(/d7) 64 p2_6 an2_6 a6(/d6) 65 p2_5 an2_5 a5(/d5) 66 p2_4 an2_4 a4(/d4) 67 p2_3 an2_3 a3(/d3) 68 p2_2 an2_2 a2(/d2) 69 p2_1 an2_1 a1(/d1) 70 p2_0 an2_0 a0(/d0)/ bc0 (/d0) 71 p1_7 int5 iio0_7/iio1_7 d15 72 p1_6 int4 iio0_6/iio1_6 d14 73 p1_5 int3 iio0_5/iio1_5 d13 74 p1_4 iio0_4/iio1_4 d12 75 p1_3 iio0_3/iio1_3 d11
rej03b0254-0101 rev.1.01 mar 11, 2010 page 18 of 109 r32c/117 group 1. overview table 1.13 pin characteristics for the 100-pin package (3/3) pin no. control pin port interrupt pin timer pin uart/can module pin intelligent i/o pin analog pin bus control pin 76 p1_2 iio0_2/iio1_2 d10 77 p1_1 iio0_1/iio1_1 d9 78 p1_0 iio0_0/iio1_0 d8 79 p0_7 an0_7 d7 80 p0_6 an0_6 d6 81 p0_5 an0_5 d5 82 p0_4 an0_4 d4 83 p0_3 an0_3 d3 84 p0_2 an0_2 d2 85 p0_1 an0_1 d1 86 p0_0 an0_0 d0 87 p10_7 ki3 an_7 88 p10_6 ki2 an_6 89 p10_5 ki1 an_5 90 p10_4 ki0 an_4 91 p10_3 an_3 92 p10_2 an_2 93 p10_1 an_1 94 avss 95 p10_0 an_0 96 vref 97 avcc 98 p9_7 rxd4/scl4/stxd4 adtrg 99 p9_6 txd4/sda4/srxd4 anex1 100 p9_5 clk4 anex0
rej03b0254-0101 rev.1.01 mar 11, 2010 page 19 of 109 r32c/117 group 1. overview 1.5 pin definitions and functions table 1.14 to table 1.18 show the pin definitions and functions. notes: 1. pins int6 to int8 are available in the 144-pin package only. 2. pins d16 to d31 are available in the 144-pin package only. table 1.14 pin definitions and functions (1/4) function symbol i/o description power supply vcc, vss i applicable as fo llows: vcc = 3.0 to 5.5 v, vss = 0 v connecting pins for decoupling capacitor vdc0, vdc1 ? a decoupling capacitor for internal voltage should be connected between vdc0 and vdc1 analog power supply avcc, avss i power supply for the a/d converter. avcc and avss should be connected to vcc and vss, respectively reset input reset i the mcu is reset when this pin is driven low cnvss cnvss i this pin should be connected to vss via a resistor debug port nsd i/o this pin is to communicate with a debugger. it should be connected to vcc via a resistor of 1 to 4.7 k main clock input xin i input/output for the ma in clock oscillator. a crystal, or a ceramic resonator should be connected between pins xin and xout. an external clock should be input at the xin while leaving the xout open main clock output xout o sub clock input xcin i input/output for the sub clock os cillator. a crystal oscillator should be connected between pins xcin and xcout. an external clock should be input at the xcin while leaving the xcout open sub clock output xcout o bclk output bclk o bclk output clock output clkout o output of the clock with the same frequency as fc, f8, or f32 external interrupt input int0 to int8 (1) i input for external interrupts nmi input p8_5/ nmi i input for nmi key input interrupt ki0 to ki3 i input for the key input interrupt bus control pins d0 to d7 i/o input/output of data (d0 to d7) while accessing an external memory space with a separate bus d8 to d15 i/o input/output of data (d8 to d15) while accessing an external memory space with 16-bit or 32-bit separate bus d16 to d31 (2) i/o input/output of data (d16 to d31) while accessing an external memory space with 32-bit separate bus a0 to a23 o output of ad dress bits a0 to a23 a0/d0 to a7/d7 i/o output of address bits (a0 to a7) and input/output of data (d0 to d7) by time-division while accessing an external memory space with multiplexed bus a8/d8 to a15/d15 i/o output of address bits (a8 to a15) and input/output of data (d8 to d15) by time-division while accessing an external memory space with 16-bit or 32-bit multiplexed bus
rej03b0254-0101 rev.1.01 mar 11, 2010 page 20 of 109 r32c/117 group 1. overview note: 1. pins bc2 /d1, wr2 , wr3 , bc2 , and bc3 are available in the 144-pin package only. table 1.15 pin definitions and functions (2/4) function symbol i/o description bus control pins bc0 /d0, bc2 / d1 (1) i/o output of byte control ( bc0 and bc2 ) and input/output of data (d0 and d1) by time-division while accessing an external memory space with multiplexed bus cs0 to cs3 o chip select output wr0 / wr1 / wr2 / wr3 wr / bc0 / bc1 / bc2 / bc3 rd (1) o output of write, byte control, and read signals. either wrx or wr and bcx can be selected by a program. data is read when rd is low. ? when wr0 , wr1 , wr2 , wr3 , and rd are selected, data is written to the following address: 4n+0, when wr0 is low 4n+1, when wr1 is low 4n+2, when wr2 is low 4n+3, when wr3 is low on 32-bit external data bus or an even address, when wr0 is low an odd address, when wr1 is low on 16-bit external data bus ? when wr , bc0 , bc1 , bc2 , bc3 , and rd are selected, data is written, when wr is low and the following address is accessed: 4n+0, when bc0 is low 4n+1, when bc1 is low 4n+2, when bc2 is low 4n+3, when bc3 is low on 32-bit external data bus or an even address, when bc0 is low an odd address, when bc1 is low on 16-bit external data bus ale o latch enable signal in multiplexed bus format hold i the mcu is in a hold state while this pin is held low hlda o this pin is driven low while the mcu is held in a hold state rdy i bus cycle is extended by the cpu if this pin is low on the falling edge of the bclk
rej03b0254-0101 rev.1.01 mar 11, 2010 page 21 of 109 r32c/117 group 1. overview notes: 1. port p9_1 in the 100-pin package is an input-only port. 2. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. table 1.16 pin definitions and functions (3/4) function symbol i/o description i/o port (1, 2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 i/o i/o ports in cmos. each port can be programmed to input or output under the control of the direction register. some ports are 5 v tolerant inputs. pull-up resistors and n-channel open drain setting can be enabled on some ports. refer to table 1.18 ?pin specifications? for details input port (2) p9_1 (for 100-pin package) p14_1 (for 144- pin package) i input port in cmos pull-up resistor is selectable. refer to table 1.18 ?pin specifications? for details timer a ta0out to ta4out i/o timers a0 to a4 input/output ta0in to ta4in i timers a0 to a4 input timer b tb0in to tb5in i timers b0 to b5 input three-phase motor control timer output u, u ,v, v ,w, w o three-phase motor control timer output serial interface cts0 to cts8 i handshake input rts0 to rts8 o handshake output clk0 to clk8 i/o transmit/receive clock input/output rxd0 to rxd8 i serial data input txd0 to txd8 o serial data output i 2 c bus (simplified) sda0 to sda6 i/o seria l data input/output scl0 to scl6 i/o transmit/receive clock input/output serial interface special functions stxd0 to stxd6 o serial data output in slave mode srxd0 to srxd6 i serial data input in slave mode ss0 to ss6 i input to control serial interface special functions
rej03b0254-0101 rev.1.01 mar 11, 2010 page 22 of 109 r32c/117 group 1. overview notes: 1. pins an15_0 to an15_7 are available in the 144-pin package only. 2. pins outc2_3 to outc2_7 are available in the 144-pin package only. table 1.17 pin definitions and functions (4/4) function symbol i/o description a/d converter an_0 to an_7, an0_0 to an0_7, an2_0 to an2_7, an15_0 to an15_7 (1) i analog input for the a/d converter adtrg i external trigger input for the a/d converter anex0 i/o expanded analog input for the a/d converter and output in external op-amp connection mode anex1 i expanded analog input for the a/d converter d/a converter da0, da1 o output for the d/a converter reference voltage input vref i reference voltage input for the a/d converter and d/a converter intelligent i/o iio0_0 to iio0_7 i/o input/output for the intelligent i/o group 0. either input capture or output compare is selectable iio1_0 to iio1_7 i/o input/output for the intelligent i/o group 1. either input capture or output compare is selectable ud0a, ud0b, ud1a, ud1b i input for the two-phase encoder outc2_0 to outc2_7 (2) o output for oc (output compare) of th e intelligent i/o group 2 isclk2 i/o clock input/output for the serial interface isrxd2 i receive data input for the serial interface istxd2 o transmit data output for the serial interface iein i receive data input for the serial interface ieout o transmit data output for the serial interface multi-master i 2 c- bus msda i/o serial data input/output mscl i/o transmit/receive clock input/output can module can0in i receive data input for the can communications can0out o transmit data output for the can communications can0wu i input for the can wake-up interrupt
rej03b0254-0101 rev.1.01 mar 11, 2010 page 23 of 109 r32c/117 group 1. overview table 1.18 pin specifications notes: 1. pull-up resistors are selected in 4-pin units, but are only enabled for those pins set as input ports. 2. n-channel open drain output can be enabled on the applicable pins on a discrete pin basis. 3. 5 v tolerant input is enabled when an applicable pin is set as an input port. when it is set as an i/o port, to enable 5 v tolerant input, this pin should be set as n-channel open drain output. pin names package selectable functions 5 v tolerant input (3) 144- pin 100- pin pull-up resistor (1) n-channel open drain (2) p0_0 to p0_7 33 3 p1_0 to p1_7 33 3 p2_0 to p2_7 33 3 p3_0 to p3_7 33 3 p4_0 to p4_7 33 3 3 p5_0 to p5_3 33 3 p5_4 to p5_7 33 3 3 p6_0 to p6_7 33 3 3 p7_0 to p7_7 33 3 3 p8_0 to p8_3 33 3 3 p8_4, p8_6, p8_7 33 3 p9_0 to p9_3 (144-pin) 333 p9_1, p9_3 (100-pin) 33 p9_4 to p9_7 33 3 3 p10_0 to p10_7 33 3 p11_0 to p11_3 333 p11_4 33 p12_0 to p12_3 333 p12_4 to p12_7 33 p13_0 to p13_7 33 p14_1, p14_3 33 p14_4 to p14_6 33 p15_0 to p15_7 333
rej03b0254-0101 rev.1.01 mar 11, 2010 page 24 of 109 r32c/117 group 2. central processing unit (cpu) 2. central processi ng unit (cpu) the cpu contains registers as shown below. there are two register banks each consisting of registers r2r0, r3r1, r6r4, r7r5, a0 to a3, sb, and fb. figure 2.1 cpu registers dda0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dcr0 dct0 dmd0 b0 b31 vct svp svf pc intb usp isp fb sb a3 a2 a1 r5 r7 r6 r4 r1l r1h r3l r3h r2h r2l r0h r0l a0 flg b0 b31 general purpose registers fast interrupt registers dmac-associated registers (2) notes: 1. there are two banks of these registers. 2. there are four identical sets of dmac-associated registers. dma destination address reload register flag register data registers (1) address registers (1) static base register (1) frame base register (1) user stack pointer interrupt stack pointer interrupt vector table base register program counter save flag register save pc register vector register r2r0 r3r1 r6r4 r7r5 dma source address register dma source address reload register dma terminal count reload register dma terminal count register dma mode register c d z s b o i u ipl rnd b0 b31 b8 b7 b16 b15 b0 b31 b23 b15 b7 dma destination address register blank fields represent reserved. fu fo dp b24 b23 b23
rej03b0254-0101 rev.1.01 mar 11, 2010 page 25 of 109 r32c/117 group 2. central processing unit (cpu) 2.1 general purpose registers 2.1.1 data registers (r2r0, r3r1, r6r4, and r7r5) these 32-bit registers are primarily used fo r transfers and arithmetic/logic operations. each of the registers can be divided into upper and lo wer 16-bit registers, e.g. r2r0 can be divided into r2 and r0, r3r0 can be divided into r3 and r1, etc. moreover, data registers r2r0 and r3r1 can be divided into four 8-bit data registers: upper (r2h and r3h), mid-upper (r2l and r3l), mid-lower (r0h and r1h), and lower (r0l and r1l). 2.1.2 address registers (a0, a1, a2, and a3) these 32-bit registers have functions similar to data registers. they are also used for address register indirect addressing and address register relative addressing. 2.1.3 static base register (sb) this 32-bit register is used for sb relative addressing. 2.1.4 frame base register (fb) this 32-bit register is used for fb relative addressing. 2.1.5 program counter (pc) this 32-bit counter indicates the address of the instruction to be executed next. 2.1.6 interrupt vector ta ble base register (intb) this 32-bit register indicates the star t address of a relocatable vector table. 2.1.7 user stack pointer (usp) a nd interrupt stack pointer (isp) two types of 32-bit stack pointers (sps) are provi ded: user stack pointer (usp) and interrupt stack pointer (isp). use the stack pointer select flag (u flag) to select either the user stack point er (usp) or the interrupt stack pointer (isp). the u flag is bit 7 in the flag re gister (flg). refer to 2.1.8 ?flag register (flg)? for details. to minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer (usp) or the interrupt stack pointer (isp) to a multiple of 4. 2.1.8 flag register (flg) this 32-bit register indicates the cpu status. 2.1.8.1 carry flag (c flag) this flag becomes 1 when any of the carry, borrow, sh ifted-out bit, etc. is generated in the arithmetic logic unit (alu). 2.1.8.2 debug flag (d flag) this flag is only for debugging. only set this bit to 0. 2.1.8.3 zero flag (z flag) this flag becomes 1 when the result of an operation is 0; otherwise it is 0. 2.1.8.4 sign flag (s flag) this flag becomes 1 when the result of an opera tion is a negative value; otherwise it is 0.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 26 of 109 r32c/117 group 2. central processing unit (cpu) 2.1.8.5 register bank se lect flag (b flag) this flag selects a register bank. it indicates 0 when the register bank 0 is selected, and 1 when the register bank 1 is selected. 2.1.8.6 overflow flag (o flag) this flag becomes 1 if an overflow occurs in an operation; otherwise it is 0. 2.1.8.7 interrupt enab le flag (i flag) this flag enables maskable interrupts. to disable mask able interrupts, set this flag to 0. to enable them, set this flag to 1. when an in terrupt is accepted, the flag becomes 0. 2.1.8.8 stack pointer se lect flag (u flag) to select the interrupt stac k pointer (isp), set this flag to 0. to select the user stack pointer (usp), set this flag to 1. it becomes 0 when a hardware interrupts is accepted or when an int instruction designated by a software interrupt number from 0 to 127 is executed. 2.1.8.9 floating-point u nderflow flag (fu flag) this flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. it also becomes 1 when the operand has invalid numbers (subnormal numbers). 2.1.8.10 floating-point o verflow flag (fo flag) this flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. it also becomes 1 when the operand has invalid numbers (subnormal numbers). 2.1.8.11 processor interrup t priority level (ipl) the processor interrupt priority leve l (ipl), consisting of three bits, selects a processor interrupt priority level from level 0 to 7. an interrupt is accept able when the interrupt request level is higher than the selected ipl. when the processor interrupt priority level (ipl) is set to 111b (level 7), all interrupts are disabled. 2.1.8.12 fixed-point radix po int designation bit (dp bit) this bit designates the radix point. it also specifies which portion of the fixed-point multiplication result to take. it is used in the mulx instruction. 2.1.8.13 floating-point rounding mode (rnd) the 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results. 2.1.8.14 reserved only set this bit to 0. the read value is undefined.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 27 of 109 r32c/117 group 2. central processing unit (cpu) 2.2 fast interrupt registers the following three registers are provided to minimize the overhead of interrupt sequence. 2.2.1 save flag register (svf) this 32-bit register is used to save the flag register when a fast interrupt is generated. 2.2.2 save pc register (svp) this 32-bit register is used to save the prog ram counter when a fast interrupt is generated. 2.2.3 vector register (vct) this 32-bit register is used to indicate a ju mp address when a fast interrupt is generated. 2.3 dmac-associated registers there are seven types of dmac-associated registers. 2.3.1 dma mode registers (d md0, dmd1, dmd2, and dmd3) these 32-bit registers are used to set dma transfer mode, bit rate etc. 2.3.2 dma terminal count register s (dct0, dct1, dct2, and dct3) these 24-bit registers are used to set dma transfer counting. 2.3.3 dma terminal count reload regi sters (dcr0, dcr1 , dcr2, and dcr3) these 24-bit registers are used to set the relo aded values for dma terminal count registers. 2.3.4 dma source address register s (dsa0, dsa1, dsa2, and dsa3) these 32-bit registers are used to set dma source addresses. 2.3.5 dma source address reload regi sters (dsr0, dsr1, dsr2, and dsr3) these 32-bit registers are used to set the reloaded value for dma source address register. 2.3.6 dma destination a ddress registers (dda0, dda1, dda2, and dda3) these 32-bit registers are used to set dma destination address. 2.3.7 dma destination address reload registers (ddr0, ddr1, ddr2, and ddr3) these 32-bit registers are used to set reloaded values for dma destination address registers.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 28 of 109 r32c/117 group 3. memory 3. memory figure 3.1 shows the memory map of the r32c/117 group. the r32c/117 group provides a 4-gbyte address space from 00000000h to ffffffffh. the internal rom is mapped to the end of the memory map with the ending address fixed at ffffffffh. therefore, the 1-mbyte internal rom is mapped from fff00000h to ffffffffh. the fixed interrupt vector table which contains each start address of interrupt handlers is mapped from ffffffdch to ffffffffh. the internal ram is mapped to the beginning of the memory map with the starting address fixed at 00000400h. therefore, the 63-kbyte internal ram is mapped from 00000400h to 0000ffffh. besides being used for data storage, the internal ram functions as a stack(s) for subroutines and/or interrupt handlers. special function registers (sfrs), which are contro l registers for peripheral functions, are mapped from 00000000h to 000003ffh, and from 00040000h to 0004ffffh. unoccupied sfr locations are reserved. no access is allowed. in memory expansion mode or microprocessor mode, so me spaces are reserved for internal use and should not be accessed. figure 3.1 memory map internal ram sfr1 sfr2 00000000h ffffffffh reset nmi reserved reserved reserved brk instruction overflow undefined instruction watchdog timer (5) ffffffffh ffffffdch yyyyyyyyh 00000400h xxxxxxxxh reserved 00040000h internal rom (data space) (1) 00060000h 00062000h 00050000h reserved internal ram capacity xxxxxxxxh 63 kbytes 00010000h 40 kbytes 0000a400h internal rom capacity yyyyyyyyh 512 kbytes fff80000h 640 kbytes fff60000h 768 kbytes fff40000h 1 mbyte fff00000h 48 kbytes 0000c400h external space (2) reserved 00080000h reserved (3) ffe00000h internal rom (4) 384 kbytes fffa0000h notes: 1. additional two 4-kbyte spaces (blocks a and b) for storing data are provided in the flash memory version. 2. this space can be used in memory expansion mode or microprocessor mode. addresses from 02000000h to fdffffffh are inaccessible. 3. this space is reserved in memory expansion mo de. it can be external space in microprocessor mode. 4. this space can be used in single-chip mode or memory expansion mode. it can be external space in microprocessor mode. 5. the watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low voltage detection interrupt. 20 kbytes 00005400h 256 kbytes fffc0000h 128 kbytes fffe0000h
rej03b0254-0101 rev.1.01 mar 11, 2010 page 29 of 109 r32c/117 group 4. special function registers (sfrs) 4. special function registers (sfrs) sfrs are memory-mapped peripheral registers that c ontrol the operation of peripherals. table 4.1 sfr list (1) to table 4.39 sfr list (39) list the sfr details. table 4.1 sfr list (1) address register symbol reset value 000000h 000001h 000002h 000003h 000004h clock control register ccr 0001 1000b 000005h 000006h flash memory control register fmcr 0000 0001b 000007h protect release register prr 00h 000008h 000009h 00000ah 00000bh 00000ch 00000dh 00000eh 00000fh 000010h external bus control register 3/flash memory rewrite bus control register 3 ebc3/febc3 0000h 000011h 000012h chip selects 2 and 3 boundary setting register cb23 00h 000013h 000014h external bus control register 2 ebc2 0000h 000015h 000016h chip selects 1 and 2 boundary setting register cb12 00h 000017h 000018h external bus control register 1 ebc1 0000h 000019h 00001ah chip selects 0 and 1 boundary setting register cb01 00h 00001bh 00001ch external bus control register 0/flash memory rewrite bus control register 0 ebc0/febc0 0000h 00001dh 00001eh peripheral bus control register pbc 0504h 00001fh 000020h to 00005fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 30 of 109 r32c/117 group 4. special function registers (sfrs) table 4.2 sfr list (2) address register symbol reset value 000060h 000061h timer b5 interrupt control register tb5ic xxxx x000b 000062h uart5 transmit/nack interrupt control register s5tic xxxx x000b 000063h uart2 receive/ack interrupt control register/i 2 c bus line interrupt control register s2ric/i2clic xxxx x000b 000064h uart6 transmit/nack interrupt control register s6tic xxxx x000b 000065h uart3 receive/ack interrupt control register s3ric xxxx x000b 000066h uart5/6 bus collision, start condition/stop condition detection interrupt control register bcn5ic/bcn6ic xxxx x000b 000067h uart4 receive/ack interrupt control register s4ric xxxx x000b 000068h dma0 transfer complete interr upt control register dm0ic xxxx x000b 000069h uart0/3 bus collision, start condition/stop condition detection interrupt control register bcn0ic/bcn3ic xxxx x000b 00006ah dma2 transfer complete interr upt control register dm2ic xxxx x000b 00006bh a/d converter 0 convert comple tion interrupt control register ad0ic xxxx x000b 00006ch timer a0 interrupt co ntrol register ta0ic xxxx x000b 00006dh intelligent i/o interrupt c ontrol register 0 iio0ic xxxx x000b 00006eh timer a2 interrupt control register ta2ic xxxx x000b 00006fh intelligent i/o interrupt c ontrol register 2 iio2ic xxxx x000b 000070h timer a4 interrupt control register ta4ic xxxx x000b 000071h intelligent i/o interrupt c ontrol register 4 iio4ic xxxx x000b 000072h uart0 receive/ack interrupt control register s0ric xxxx x000b 000073h intelligent i/o interrupt c ontrol register 6 iio6ic xxxx x000b 000074h uart1 receive/ack interrupt control register s1ric xxxx x000b 000075h intelligent i/o interrupt c ontrol register 8 iio8ic xxxx x000b 000076h timer b1 interrupt control register tb1ic xxxx x000b 000077h intelligent i/o interrupt cont rol register 10 iio10ic xxxx x000b 000078h timer b3 interrupt control register tb3ic xxxx x000b 000079h 00007ah int5 interrupt control register int5ic xx00 x000b 00007bh can0 wake-up interrupt control register c0wic xxxx x000b 00007ch int3 interrupt control register int3ic xx00 x000b 00007dh 00007eh int1 interrupt control register int1ic xx00 x000b 00007fh 000080h 000081h uart2 transmit/nack interru pt control register/i 2 c-bus interrupt control register s2tic/i2cic xxxx x000b 000082h uart5 receive/ack interrupt control register s5ric xxxx x000b 000083h uart3 transmit/nack interrupt control register s3tic xxxx x000b 000084h uart6 receive/ack interrupt control register s6ric xxxx x000b 000085h uart4 transmit/nack interrupt control register s4tic xxxx x000b 000086h 000087h uart2 bus collision, start condition/stop condition detection interrupt control register bcn2ic xxxx x000b x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 31 of 109 r32c/117 group 4. special function registers (sfrs) table 4.3 sfr list (3) address register symbol reset value 000088h dma1 transfer complete interr upt control register dm1ic xxxx x000b 000089h uart1/4 bus collision, start condition/stop condition detection interrupt control register bcn1ic/bcn4ic xxxx x000b 00008ah dma3 transfer complete interr upt control register dm3ic xxxx x000b 00008bh key input interrupt control register kupic xxxx x000b 00008ch timer a1 interrupt co ntrol register ta1ic xxxx x000b 00008dh intelligent i/o interrupt c ontrol register 1 iio1ic xxxx x000b 00008eh timer a3 interrupt control register ta3ic xxxx x000b 00008fh intelligent i/o interrupt c ontrol register 3 iio3ic xxxx x000b 000090h uart0 transmit/nack interrupt control register s0tic xxxx x000b 000091h intelligent i/o interrupt c ontrol register 5 iio5ic xxxx x000b 000092h uart1 transmit/nack interrupt control register s1tic xxxx x000b 000093h intelligent i/o interrupt c ontrol register 7 iio7ic xxxx x000b 000094h timer b0 interrupt control register tb0ic xxxx x000b 000095h intelligent i/o interrupt c ontrol register 9 iio9ic xxxx x000b 000096h timer b2 interrupt control register tb2ic xxxx x000b 000097h intelligent i/o interrupt cont rol register 11 iio11ic xxxx x000b 000098h timer b4 interrupt control register tb4ic xxxx x000b 000099h 00009ah int4 interrupt control register int4ic xx00 x000b 00009bh 00009ch int2 interrupt control register int2ic xx00 x000b 00009dh 00009eh int0 interrupt control register int0ic xx00 x000b 00009fh 0000a0h intelligent i/o interrupt requ est register 0 iio0ir 0000 0xx1b 0000a1h intelligent i/o interrupt requ est register 1 iio1ir 0000 0xx1b 0000a2h intelligent i/o interrupt requ est register 2 iio2ir 0000 0x01b 0000a3h intelligent i/o interrupt requ est register 3 iio3ir 0000 xxx1b 0000a4h intelligent i/o interrupt requ est register 4 iio4ir 000x 0xx1b 0000a5h intelligent i/o interrupt requ est register 5 iio5ir 000x 0xx1b 0000a6h intelligent i/o interrupt requ est register 6 iio6ir 000x 0xx1b 0000a7h intelligent i/o interrupt requ est register 7 iio7ir x00x 0xx1b 0000a8h intelligent i/o interrupt requ est register 8 iio8ir xx0x 0xx1b 0000a9h intelligent i/o interrupt requ est register 9 iio9ir 0x00 0xx1b 0000aah intelligent i/o interrupt requ est register 10 iio10ir 0x00 0xx1b 0000abh intelligent i/o interrupt request register 11 iio11ir 0x00 0xx1b 0000ach 0000adh 0000aeh 0000afh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 32 of 109 r32c/117 group 4. special function registers (sfrs) table 4.4 sfr list (4) address register symbol reset value 0000b0h intelligent i/o interrupt enable register 0 iio0ie 00h 0000b1h intelligent i/o interrupt enable register 1 iio1ie 00h 0000b2h intelligent i/o interrupt enable register 2 iio2ie 00h 0000b3h intelligent i/o interrupt enable register 3 iio3ie 00h 0000b4h intelligent i/o interrupt enable register 4 iio4ie 00h 0000b5h intelligent i/o interrupt enable register 5 iio5ie 00h 0000b6h intelligent i/o interrupt enable register 6 iio6ie 00h 0000b7h intelligent i/o interrupt enable register 7 iio7ie 00h 0000b8h intelligent i/o interrupt enable register 8 iio8ie 00h 0000b9h intelligent i/o interrupt enable register 9 iio9ie 00h 0000bah intelligent i/o interrupt enable register 10 iio10ie 00h 0000bbh intelligent i/o interrupt enable register 11 iio11ie 00h 0000bch 0000bdh 0000beh 0000bfh 0000c0h 0000c1h can0 transmit interrupt control r egister c0tic xxxx x000b 0000c2h 0000c3h can0 error interrupt co ntrol register c0eic xxxx x000b 0000c4h 0000c5h 0000c6h 0000c7h 0000c8h 0000c9h 0000cah 0000cbh 0000cch 0000cdh 0000ceh 0000cfh 0000d0h can0 transmit fi fo interrupt co ntrol register c0ftic xxxx x000b 0000d1h 0000d2h 0000d3h 0000d4h 0000d5h 0000d6h 0000d7h 0000d8h 0000d9h 0000dah 0000dbh 0000dch 0000ddh uart7 transmit interrupt control register s7tic xxxx x000b 0000deh int7 interrupt control register int7ic xx00 x000b 0000dfh uart8 transmit interrupt control register s8tic xxxx x000b x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 33 of 109 r32c/117 group 4. special function registers (sfrs) table 4.5 sfr list (5) address register symbol reset value 0000e0h 0000e1h can0 receive interrupt control register c0ric xxxx x000b 0000e2h 0000e3h 0000e4h 0000e5h 0000e6h 0000e7h 0000e8h 0000e9h 0000eah 0000ebh 0000ech 0000edh 0000eeh 0000efh 0000f0h can0 receive fi fo interrupt control register c0fric xxxx x000b 0000f1h 0000f2h 0000f3h 0000f4h 0000f5h 0000f6h 0000f7h 0000f8h 0000f9h 0000fah 0000fbh 0000fch int8 interrupt control register int8ic xx00 x000b 0000fdh uart7 receive interrupt control r egister s7ric xxxx x000b 0000feh int6 interrupt control register int6ic xx00 x000b 0000ffh uart8 receive interrupt control register s8ric xxxx x000b 000100h group 1 time measurement/waveform generation register 0 g1tm0/g1po0 xxxxh 000101h 000102h group 1 time measurement/waveform generation register 1 g1tm1/g1po1 xxxxh 000103h 000104h group 1 time measurement/waveform generation register 2 g1tm2/g1po2 xxxxh 000105h 000106h group 1 time measurement/waveform generation register 3 g1tm3/g1po3 xxxxh 000107h x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 34 of 109 r32c/117 group 4. special function registers (sfrs) table 4.6 sfr list (6) address register symbol reset value 000108h group 1 time measurement/waveform generation register 4 g1tm4/g1po4 xxxxh 000109h 00010ah group 1 time measurement/waveform generation register 5 g1tm5/g1po5 xxxxh 00010bh 00010ch group 1 time measur ement/waveform generation register 6 g1tm6/g1po6 xxxxh 00010dh 00010eh group 1 time measurement/waveform generation register 7 g1tm7/g1po7 xxxxh 00010fh 000110h group 1 waveform generation control register 0 g1pocr0 0000 x000b 000111h group 1 waveform generation control register 1 g1pocr1 0x00 x000b 000112h group 1 waveform generation control register 2 g1pocr2 0x00 x000b 000113h group 1 waveform generation control register 3 g1pocr3 0x00 x000b 000114h group 1 waveform generation control register 4 g1pocr4 0x00 x000b 000115h group 1 waveform generation control register 5 g1pocr5 0x00 x000b 000116h group 1 waveform generation control register 6 g1pocr6 0x00 x000b 000117h group 1 waveform generation control register 7 g1pocr7 0x00 x000b 000118h group 1 time measurement control register 0 g1tmcr0 00h 000119h group 1 time measurement control register 1 g1tmcr1 00h 00011ah group 1 time measurement control register 2 g1tmcr2 00h 00011bh group 1 time measurement control register 3 g1tmcr3 00h 00011ch group 1 time measurement control register 4 g1tmcr4 00h 00011dh group 1 time measurement control register 5 g1tmcr5 00h 00011eh group 1 time measurement control register 6 g1tmcr6 00h 00011fh group 1 time measurement control register 7 g1tmcr7 00h 000120h group 1 base timer register g1bt xxxxh 000121h 000122h group 1 base timer control register 0 g1bcr0 00h 000123h group 1 base timer control register 1 g1bcr1 0000 0000b 000124h group 1 timer measurement prescaler register 6 g1tpr6 00h 000125h group 1 timer measurement prescaler register 7 g1tpr7 00h 000126h group 1 function enable register g1fe 00h 000127h group 1 function select register g1fs 00h 000128h 000129h 00012ah 00012bh 00012ch 00012dh 00012eh 00012fh 000130h to 00013fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 35 of 109 r32c/117 group 4. special function registers (sfrs) table 4.7 sfr list (7) address register symbol reset value 000140h group 2 waveform generation register 0 g2po0 xxxxh 000141h 000142h group 2 waveform generation register 1 g2po1 xxxxh 000143h 000144h group 2 waveform generation register 2 g2po2 xxxxh 000145h 000146h group 2 waveform generation register 3 g2po3 xxxxh 000147h 000148h group 2 waveform generation register 4 g2po4 xxxxh 000149h 00014ah group 2 waveform generation register 5 g2po5 xxxxh 00014bh 00014ch group 2 waveform gene ration register 6 g2po6 xxxxh 00014dh 00014eh group 2 waveform generation register 7 g2po7 xxxxh 00014fh 000150h group 2 waveform generation control register 0 g2pocr0 0000 0000b 000151h group 2 waveform generation control register 1 g2pocr1 0000 0000b 000152h group 2 waveform generation control register 2 g2pocr2 0000 0000b 000153h group 2 waveform generation control register 3 g2pocr3 0000 0000b 000154h group 2 waveform generation control register 4 g2pocr4 0000 0000b 000155h group 2 waveform generation control register 5 g2pocr5 0000 0000b 000156h group 2 waveform generation control register 6 g2pocr6 0000 0000b 000157h group 2 waveform generation control register 7 g2pocr7 0000 0000b 000158h 000159h 00015ah 00015bh 00015ch 00015dh 00015eh 00015fh 000160h group 2 base timer register g2bt xxxxh 000161h 000162h group 2 base timer control register 0 g2bcr0 00h 000163h group 2 base timer control register 1 g2bcr1 0000 0000b 000164h base timer start register btsr xxxx 0000b 000165h 000166h group 2 function enable register g2fe 00h 000167h group 2 rtp output buffer register g2rtp 00h 000168h 000169h 00016ah group 2 serial interface mode register g2mr 00xx x000b 00016bh group 2 serial interface control register g2cr 0000 x110b 00016ch group 2 si/o transmit buffer register g2tb xxxxh 00016dh 00016eh group 2 si/o receive buffer register g2rb xxxxh 00016fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 36 of 109 r32c/117 group 4. special function registers (sfrs) table 4.8 sfr list (8) address register symbol reset value 000170h group 2 ie bus address register iear xxxxh 000171h 000172h group 2 ie bus control register iecr 00xx x000b 000173h group 2 ie bus transmit interrupt source detect register ietif xxx0 0000b 000174h group 2 ie bus receive interrupt source detect register ierif xxx0 0000b 000175h 000176h 000177h 000178h 000179h 00017ah 00017bh 00017ch 00017dh 00017eh 00017fh 000180h group 0 time measurement/waveform generation register 0 g0tm0/g0po0 xxxxh 000181h 000182h group 0 time measurement/waveform generation register 1 g0tm1/g0po1 xxxxh 000183h 000184h group 0 time measurement/waveform generation register 2 g0tm2/g0po2 xxxxh 000185h 000186h group 0 time measurement/waveform generation register 3 g0tm3/g0po3 xxxxh 000187h 000188h group 0 time measurement/waveform generation register 4 g0tm4/g0po4 xxxxh 000189h 00018ah group 0 time measurement/waveform generation register 5 g0tm5/g0po5 xxxxh 00018bh 00018ch group 0 time measur ement/waveform generation register 6 g0tm6/g0po6 xxxxh 00018dh 00018eh group 0 time measurement/waveform generation register 7 g0tm7/g0po7 xxxxh 00018fh 000190h group 0 waveform generation control register 0 g0pocr0 0000 x000b 000191h group 0 waveform generation control register 1 g0pocr1 0x00 x000b 000192h group 0 waveform generation control register 2 g0pocr2 0x00 x000b 000193h group 0 waveform generation control register 3 g0pocr3 0x00 x000b 000194h group 0 waveform generation control register 4 g0pocr4 0x00 x000b 000195h group 0 waveform generation control register 5 g0pocr5 0x00 x000b 000196h group 0 waveform generation control register 6 g0pocr6 0x00 x000b 000197h group 0 waveform generation control register 7 g0pocr7 0x00 x000b 000198h group 0 time measurement control register 0 g0tmcr0 00h 000199h group 0 time measurement control register 1 g0tmcr1 00h 00019ah group 0 time measurement control register 2 g0tmcr2 00h 00019bh group 0 time measurement control register 3 g0tmcr3 00h 00019ch group 0 time measurement control register 4 g0tmcr4 00h 00019dh group 0 time measurement control register 5 g0tmcr5 00h 00019eh group 0 time measurement control register 6 g0tmcr6 00h 00019fh group 0 time measurement control register 7 g0tmcr7 00h x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 37 of 109 r32c/117 group 4. special function registers (sfrs) table 4.9 sfr list (9) address register symbol reset value 0001a0h group 0 base timer register g0bt xxxxh 0001a1h 0001a2h group 0 base timer control register 0 g0bcr0 00h 0001a3h group 0 base timer control register 1 g0bcr1 0000 0000b 0001a4h group 0 timer measurement prescaler register 6 g0tpr6 00h 0001a5h group 0 timer measurement prescaler register 7 g0tpr7 00h 0001a6h group 0 function enable register g0fe 00h 0001a7h group 0 function select register g0fs 00h 0001a8h 0001a9h 0001aah 0001abh 0001ach 0001adh 0001aeh 0001afh 0001b0h 0001b1h 0001b2h 0001b3h 0001b4h 0001b5h 0001b6h 0001b7h 0001b8h 0001b9h 0001bah 0001bbh 0001bch 0001bdh 0001beh 0001bfh 0001c0h 0001c1h 0001c2h 0001c3h 0001c4h uart5 special mode register 4 u5smr4 00h 0001c5h uart5 special mode register 3 u5smr3 00h 0001c6h uart5 special mode register 2 u5smr2 00h 0001c7h uart5 special mode register u5smr 00h 0001c8h uart5 transmit/receive mode register u5mr 00h 0001c9h uart5 bit ra te register u5brg xxh 0001cah uart5 transmit buffer register u5tb xxxxh 0001cbh 0001cch uart5 transmit/receive control register 0 u5c0 0000 1000b 0001cdh uart5 transmit/receive control register 1 u5c1 0000 0010b 0001ceh uart5 receive buffer register u5rb xxxxh 0001cfh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 38 of 109 r32c/117 group 4. special function registers (sfrs) table 4.10 sfr list (10) address register symbol reset value 0001d0h 0001d1h 0001d2h 0001d3h 0001d4h uart6 special mode register 4 u6smr4 00h 0001d5h uart6 special mode register 3 u6smr3 00h 0001d6h uart6 special mode register 2 u6smr2 00h 0001d7h uart6 special mode register u6smr 00h 0001d8h uart6 transmit/receive mode register u6mr 00h 0001d9h uart6 bit ra te register u6brg xxh 0001dah uart6 transmit buffer register u6tb xxxxh 0001dbh 0001dch uart6 transmit/receive control register 0 u6c0 0000 1000b 0001ddh uart6 transmit/receive control register 1 u6c1 0000 0010b 0001deh uart6 receive buffer register u6rb xxxxh 0001dfh 0001e0h uart7 transmit/receive mode register u7mr 00h 0001e1h uart7 bit rate register u7brg xxh 0001e2h uart7 transmit buffer register u7tb xxxxh 0001e3h 0001e4h uart7 transmit/receive control register 0 u7c0 00x0 1000b 0001e5h uart7 transmit/receive control register 1 u7c1 xxxx 0010b 0001e6h uart7 receive buffer register u7rb xxxxh 0001e7h 0001e8h uart8 transmit/receive mode register u8mr 00h 0001e9h uart8 bit rate register u8brg xxh 0001eah uart8 transmit buffer register u8tb xxxxh 0001ebh 0001ech uart8 transmit/receive control register 0 u8c0 00x0 1000b 0001edh uart8 transmit/receive co ntrol register 1 u8c1 xxxx 0010b 0001eeh uart8 receive buffer register u8rb xxxxh 0001efh 0001f0h uart7, uart8 transmit/receive control register 2 u78con x000 0000b 0001f1h 0001f2h 0001f3h 0001f4h 0001f5h 0001f6h 0001f7h 0001f8h 0001f9h 0001fah 0001fbh 0001fch 0001fdh 0001feh 0001ffh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 39 of 109 r32c/117 group 4. special function registers (sfrs) table 4.11 sfr list (11) address register symbol reset value 000200h to 0002bfh 0002c0h x0 register/y 0 register x0r/y0r xxxxh 0002c1h 0002c2h x1 register/y 1 register x1r/y1r xxxxh 0002c3h 0002c4h x2 register/y 2 register x2r/y2r xxxxh 0002c5h 0002c6h x3 register/y 3 register x3r/y3r xxxxh 0002c7h 0002c8h x4 register/y 4 register x4r/y4r xxxxh 0002c9h 0002cah x5 register/y 5 register x5r/y5r xxxxh 0002cbh 0002cch x6 register/y6 register x6r/y6r xxxxh 0002cdh 0002ceh x7 register/y 7 register x7r/y7r xxxxh 0002cfh 0002d0h x8 register/y 8 register x8r/y8r xxxxh 0002d1h 0002d2h x9 register/y 9 register x9r/y9r xxxxh 0002d3h 0002d4h x10 register/y10 register x10r/y10r xxxxh 0002d5h 0002d6h x11 register/y11 register x11r/y11r xxxxh 0002d7h 0002d8h x12 register/y12 register x12r/y12r xxxxh 0002d9h 0002dah x13 register/y13 register x13r/y13r xxxxh 0002dbh 0002dch x14 register/y14 register x14r/y14r xxxxh 0002ddh 0002deh x15 register/y15 register x15r/y15r xxxxh 0002dfh 0002e0h xy control register xyc xxxx xx00b 0002e1h 0002e2h 0002e3h 0002e4h uart1 special mode register 4 u1smr4 00h 0002e5h uart1 special mode register 3 u1smr3 00h 0002e6h uart1 special mode register 2 u1smr2 00h 0002e7h uart1 special mode register u1smr 00h 0002e8h uart1 transmit/receive mode register u1mr 00h 0002e9h uart1 bit rate register u1brg xxh 0002eah uart1 transmit buffer register u1tb xxxxh 0002ebh 0002ech uart1 transmit/receive control register 0 u1c0 0000 1000b 0002edh uart1 transmit/receive control register 1 u1c1 0000 0010b 0002eeh uart1 receive buffer register u1rb xxxxh 0002efh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 40 of 109 r32c/117 group 4. special function registers (sfrs) table 4.12 sfr list (12) address register symbol reset value 0002f0h 0002f1h 0002f2h 0002f3h 0002f4h uart4 special mode register 4 u4smr4 00h 0002f5h uart4 special mode register 3 u4smr3 00h 0002f6h uart4 special mode register 2 u4smr2 00h 0002f7h uart4 special mode register u4smr 00h 0002f8h uart4 transmit/receive mode register u4mr 00h 0002f9h uart4 bit rate register u4brg xxh 0002fah uart4 transmit buffer register u4tb xxxxh 0002fbh 0002fch uart4 transmit/receive control register 0 u4c0 0000 1000b 0002fdh uart4 transmit/receive control register 1 u4c1 0000 0010b 0002feh uart4 receive buffer register u4rb xxxxh 0002ffh 000300h count start register for timers b3, b4, and b5 tbsr 000x xxxxb 000301h 000302h timer a1-1 register ta11 xxxxh 000303h 000304h timer a2-1 register ta21 xxxxh 000305h 000306h timer a4-1 register ta41 xxxxh 000307h 000308h three-phase pwm control register 0 invc0 00h 000309h three-phase pwm control register 1 invc1 00h 00030ah three-phase output buffer register 0 idb0 xx11 1111b 00030bh three-phase output buffer register 1 idb1 xx11 1111b 00030ch dead time timer dtt xxh 00030dh timer b2 interrupt generating frequency set counter ictb2 xxh 00030eh 00030fh 000310h timer b3 register tb3 xxxxh 000311h 000312h timer b4 register tb4 xxxxh 000313h 000314h timer b5 register tb5 xxxxh 000315h 000316h 000317h 000318h 000319h 00031ah 00031bh timer b3 mode register tb3mr 00xx 0000b 00031ch timer b4 mode register tb4mr 00xx 0000b 00031dh timer b5 mode register tb5mr 00xx 0000b 00031eh 00031fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 41 of 109 r32c/117 group 4. special function registers (sfrs) table 4.13 sfr list (13) address register symbol reset value 000320h 000321h 000322h 000323h 000324h uart3 special mode register 4 u3smr4 00h 000325h uart3 special mode register 3 u3smr3 00h 000326h uart3 special mode register 2 u3smr2 00h 000327h uart3 special mode register u3smr 00h 000328h uart3 transmit/receive mode register u3mr 00h 000329h uart3 bit rate register u3brg xxh 00032ah uart3 transmit buffer register u3tb xxxxh 00032bh 00032ch uart3 transmit/receive control register 0 u3c0 0000 1000b 00032dh uart3 transmit/receive control register 1 u3c1 0000 0010b 00032eh uart3 receive buffer register u3rb xxxxh 00032fh 000330h 000331h 000332h 000333h 000334h uart2 special mode register 4 u2smr4 00h 000335h uart2 special mode register 3 u2smr3 00h 000336h uart2 special mode register 2 u2smr2 00h 000337h uart2 special mode register u2smr 00h 000338h uart2 transmission/receive mode register u2mr 00h 000339h uart2 bit rate register u2brg xxh 00033ah uart2 transmit buffer register u2tb xxxxh 00033bh 00033ch uart2 transmit/receive control register 0 u2c0 0000 1000b 00033dh uart2 transmit/receive control register 1 u2c1 0000 0010b 00033eh uart2 receive buffer register u2rb xxxxh 00033fh 000340h count start register tabsr 00h 000341h clock prescaler reset register cpsrf 0xxx xxxxb 000342h one-shot start register onsf 00h 000343h trigger select register trgsr 00h 000344h increment/decrement counting select register udf 0000 0000b 000345h 000346h timer a0 register ta0 xxxxh 000347h 000348h timer a1 register ta1 xxxxh 000349h 00034ah timer a2 register ta2 xxxxh 00034bh 00034ch timer a3 register ta3 xxxxh 00034dh 00034eh timer a4 register ta4 xxxxh 00034fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 42 of 109 r32c/117 group 4. special function registers (sfrs) table 4.14 sfr list (14) address register symbol reset value 000350h timer b0 register tb0 xxxxh 000351h 000352h timer b1 register tb1 xxxxh 000353h 000354h timer b2 register tb2 xxxxh 000355h 000356h timer a0 mode register ta0mr 0000 0000b 000357h timer a1 mode register ta1mr 0000 0000b 000358h timer a2 mode register ta2mr 0000 0000b 000359h timer a3 mode register ta3mr 0000 0000b 00035ah timer a4 mode register ta4mr 0000 0000b 00035bh timer b0 mode register tb0mr 00xx 0000b 00035ch timer b1 mode register tb1mr 00xx 0000b 00035dh timer b2 mode register tb2mr 00xx 0000b 00035eh timer b2 special mode register tb2sc xxxx xxx0b 00035fh count source prescaler register tcspr 0000 0000b 000360h 000361h 000362h 000363h 000364h uart0 special mode register 4 u0smr4 00h 000365h uart0 special mode register 3 u0smr3 00h 000366h uart0 special mode register 2 u0smr2 00h 000367h uart0 special mode register u0smr 00h 000368h uart0 transmit/receive mode register u0mr 00h 000369h uart0 bit rate register u0brg xxh 00036ah uart0 transmit buffer register u0tb xxxxh 00036bh 00036ch uart0 transmit/receive control register 0 u0c0 0000 1000b 00036dh uart0 transmit/receive control register 1 u0c1 0000 0010b 00036eh uart0 receive buffer register u0rb xxxxh 00036fh 000370h 000371h 000372h 000373h 000374h 000375h 000376h 000377h 000378h 000379h 00037ah 00037bh 00037ch crc data register crcd xxxxh 00037dh 00037eh crc input register crcin xxh 00037fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 43 of 109 r32c/117 group 4. special function registers (sfrs) table 4.15 sfr list (15) address register symbol reset value 000380h a/d0 register 0 ad00 00xxh 000381h 000382h a/d0 register 1 ad01 00xxh 000383h 000384h a/d0 register 2 ad02 00xxh 000385h 000386h a/d0 register 3 ad03 00xxh 000387h 000388h a/d0 register 4 ad04 00xxh 000389h 00038ah a/d0 register 5 ad05 00xxh 00038bh 00038ch a/d0 register 6 ad06 00xxh 00038dh 00038eh a/d0 register 7 ad07 00xxh 00038fh 000390h 000391h 000392h a/d0 control register 4 ad0con4 xxxx 00xxb 000393h 000394h a/d0 control register 2 ad0con2 x00x x000b 000395h a/d0 control register 3 ad0con3 xxxx x000b 000396h a/d0 control register 0 ad0con0 00h 000397h a/d0 control register 1 ad0con1 00h 000398h d/a register 0 da0 xxh 000399h 00039ah d/a register 1 da1 xxh 00039bh 00039ch d/a control register dacon xxxx xx00b 00039dh 00039eh 00039fh 0003a0h 0003a1h 0003a2h 0003a3h 0003a4h 0003a5h 0003a6h 0003a7h 0003a8h 0003a9h 0003aah 0003abh 0003ach 0003adh 0003aeh 0003afh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 44 of 109 r32c/117 group 4. special function registers (sfrs) table 4.16 sfr list (16) address register symbol reset value 0003b0h 0003b1h 0003b2h 0003b3h 0003b4h 0003b5h 0003b6h 0003b7h 0003b8h 0003b9h 0003bah 0003bbh 0003bch 0003bdh 0003beh 0003bfh 0003c0h port p0 register p0 xxh 0003c1h port p1 register p1 xxh 0003c2h port p0 direction register pd0 0000 0000b 0003c3h port p1 direction register pd1 0000 0000b 0003c4h port p2 register p2 xxh 0003c5h port p3 register p3 xxh 0003c6h port p2 direction register pd2 0000 0000b 0003c7h port p3 direction register pd3 0000 0000b 0003c8h port p4 register p4 xxh 0003c9h port p5 register p5 xxh 0003cah port p4 direction register pd4 0000 0000b 0003cbh port p5 direction register pd5 0000 0000b 0003cch port p6 register p6 xxh 0003cdh port p7 register p7 xxh 0003ceh port p6 direction register pd6 0000 0000b 0003cfh port p7 direction register pd7 0000 0000b 0003d0h port p8 register p8 xxh 0003d1h port p9 register p9 xxh 0003d2h port p8 direction register pd8 00x0 0000b 0003d3h port p9 direction register pd9 0000 0000b 0003d4h port p10 register p10 xxh 0003d5h port p11 register p11 xxh 0003d6h port p10 direction register pd10 0000 0000b 0003d7h port p11 direction register pd11 xxx0 0000b 0003d8h port p12 register p12 xxh 0003d9h port p13 register p13 xxh 0003dah port p12 direction register pd12 0000 0000b 0003dbh port p13 direction register pd13 0000 0000b 0003dch port p14 register p14 xxh 0003ddh port p15 register p15 xxh 0003deh port p14 direction register pd14 x000 0000b 0003dfh port p15 direction register pd15 0000 0000b x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 45 of 109 r32c/117 group 4. special function registers (sfrs) table 4.17 sfr list (17) address register symbol reset value 0003e0h 0003e1h 0003e2h 0003e3h 0003e4h 0003e5h 0003e6h 0003e7h 0003e8h 0003e9h 0003eah 0003ebh 0003ech 0003edh 0003eeh 0003efh 0003f0h pull-up control register 0 pur0 0000 0000b 0003f1h pull-up control register 1 pur1 xxxx x0xxb 0003f2h pull-up control register 2 pur2 000x xxxxb 0003f3h pull-up control register 3 pur3 0000 0000b 0003f4h pull-up control register 4 pur4 xxxx 0000b 0003f5h 0003f6h 0003f7h 0003f8h 0003f9h 0003fah 0003fbh 0003fch 0003fdh 0003feh 0003ffh port control register pcr 0xxx xxx0b x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 46 of 109 r32c/117 group 4. special function registers (sfrs) note: 1. the status of protect bit of each block in flash memory is reflected. table 4.18 sfr list (18) address register symbol reset value 040000h flash memory control register 0 fmr0 0x01 xx00b 040001h flash memory status register 0 fmsr0 1000 0000b 040002h 040003h 040004h 040005h 040006h 040007h 040008h flash register protection unlock register 0 fpr0 00h 040009h flash memory control register 1 fmr1 0000 0010b 04000ah block protect bit monitor register 0 fbpm0 ??x? ????b (1) 04000bh block protect bit monitor register 1 fbpm1 xxx? ????b (1) 04000ch 04000dh 04000eh 04000fh 040010h 040011h block protect bit monitor register 2 fbpm2 ???? ????b (1) 040012h 040013h 040014h 040015h 040016h 040017h 040018h 040019h 04001ah 04001bh 04001ch 04001dh 04001eh 04001fh 040020h pll control register 0 plc0 0000 0001b 040021h pll control register 1 plc1 0001 1111b 040022h 040023h 040024h 040025h 040026h 040027h 040028h 040029h 04002ah 04002bh 04002ch 04002dh 04002eh 04002fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 47 of 109 r32c/117 group 4. special function registers (sfrs) note: 1. the value in the pm0 register remains unchanged even after a software reset or watchdog timer reset. table 4.19 sfr list (19) address register symbol reset value 040030h to 04003fh 040040h 040041h 040042h 040043h 040044h processor mode register 0 (1) pm0 1000 0000b (cnvss pin = low) 0000 0011b (cnvss pin = high) 040045h 040046h system clock control register 0 cm0 0000 1000b 040047h system clock control register 1 cm1 0010 0000b 040048h processor mode register 3 pm3 00h 040049h 04004ah protect register prcr xxxx x000b 04004bh 04004ch protect register 3 prcr3 0000 0000b 04004dh oscillator stop detection register cm2 00h 04004eh 04004fh 040050h 040051h 040052h 040053h processor mode register 2 pm2 00h 040054h chip select output pin setting register 0 csop0 1000 xxxxb 040055h chip select output pin setting register 1 csop1 01x0 xxxxb 040056h chip select output pin setting register 2 csop2 xxxx 0000b 040057h 040058h 040059h 04005ah low speed mode clock control register cm3 xxxx xx00b 04005bh 04005ch 04005dh 04005eh 04005fh 040060h voltage regulator control register vrcr 0000 0000b 040061h 040062h low voltage detector control register lvdc 0000 xx00b 040063h 040064h detection voltage configuration register dvcr 0000 xxxxb 040065h 040066h 040067h 040068h to 040093h x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 48 of 109 r32c/117 group 4. special function registers (sfrs) table 4.20 sfr list (20) address register symbol reset value 040094h 040095h 040096h 040097h three-phase output buffer control register iobc 0xxx xxxxb 040098h input function select register 0 ifs0 x000 0000b 040099h input function select register 1 ifs1 xxxx x0x0b 04009ah input function select register 2 ifs2 0000 00x0b 04009bh input function select register 3 ifs3 xxxx xx00b 04009ch 04009dh 04009eh 04009fh 0400a0h port p0_0 function select register p0_0s 0xxx x000b 0400a1h port p1_0 function select register p1_0s xxxx x000b 0400a2h port p0_1 function select register p0_1s 0xxx x000b 0400a3h port p1_1 function select register p1_1s xxxx x000b 0400a4h port p0_2 function select register p0_2s 0xxx x000b 0400a5h port p1_2 function select register p1_2s xxxx x000b 0400a6h port p0_3 function select register p0_3s 0xxx x000b 0400a7h port p1_3 function select register p1_3s xxxx x000b 0400a8h port p0_4 function select register p0_4s 0xxx x000b 0400a9h port p1_4 function select register p1_4s xxxx x000b 0400aah port p0_5 function sele ct register p0_5s 0xxx x000b 0400abh port p1_5 function se lect register p1_5s xxxx x000b 0400ach port p0_6 function select register p0_6s 0xxx x000b 0400adh port p1_6 function se lect register p1_6s xxxx x000b 0400aeh port p0_7 function sele ct register p0_7s 0xxx x000b 0400afh port p1_7 function se lect register p1_7s xxxx x000b 0400b0h port p2_0 function select register p2_0s 0xxx x000b 0400b1h port p3_0 function select register p3_0s xxxx x000b 0400b2h port p2_1 function select register p2_1s 0xxx x000b 0400b3h port p3_1 function select register p3_1s xxxx x000b 0400b4h port p2_2 function select register p2_2s 0xxx x000b 0400b5h port p3_2 function select register p3_2s xxxx x000b 0400b6h port p2_3 function select register p2_3s 0xxx x000b 0400b7h port p3_3 function select register p3_3s xxxx x000b 0400b8h port p2_4 function select register p2_4s 0xxx x000b 0400b9h port p3_4 function select register p3_4s xxxx x000b 0400bah port p2_5 function sele ct register p2_5s 0xxx x000b 0400bbh port p3_5 function se lect register p3_5s xxxx x000b 0400bch port p2_6 function select register p2_6s 0xxx x000b 0400bdh port p3_6 function se lect register p3_6s xxxx x000b 0400beh port p2_7 function sele ct register p2_7s 0xxx x000b 0400bfh port p3_7 function se lect register p3_7s xxxx x000b x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 49 of 109 r32c/117 group 4. special function registers (sfrs) table 4.21 sfr list (21) address register symbol reset value 0400c0h port p4_0 function select register p4_0s x0xx x000b 0400c1h port p5_0 function se lect register p5_0s xxxx x000b 0400c2h port p4_1 function select register p4_1s x0xx x000b 0400c3h port p5_1 function se lect register p5_1s xxxx x000b 0400c4h port p4_2 function select register p4_2s x0xx x000b 0400c5h port p5_2 function se lect register p5_2s xxxx x000b 0400c6h port p4_3 function select register p4_3s x0xx x000b 0400c7h port p5_3 function se lect register p5_3s xxxx x000b 0400c8h port p4_4 function select register p4_4s x0xx x000b 0400c9h port p5_4 function select register p5_4s x0xx x000b 0400cah port p4_5 function sele ct register p4_5s x0xx x000b 0400cbh port p5_5 function sele ct register p5_5s x0xx x000b 0400cch port p4_6 function select register p4_6s x0xx x000b 0400cdh port p5_6 function select register p5_6s x0xx x000b 0400ceh port p4_7 function sele ct register p4_7s x0xx x000b 0400cfh port p5_7 function select register p5_7s x0xx x000b 0400d0h port p6_0 function select register p6_0s x0xx x000b 0400d1h port p7_0 function select register p7_0s x0xx x000b 0400d2h port p6_1 function select register p6_1s x0xx x000b 0400d3h port p7_1 function select register p7_1s x0xx x000b 0400d4h port p6_2 function select register p6_2s x0xx x000b 0400d5h port p7_2 function select register p7_2s x0xx x000b 0400d6h port p6_3 function select register p6_3s x0xx x000b 0400d7h port p7_3 function select register p7_3s x0xx x000b 0400d8h port p6_4 function select register p6_4s x0xx x000b 0400d9h port p7_4 function select register p7_4s x0xx x000b 0400dah port p6_5 function sele ct register p6_5s x0xx x000b 0400dbh port p7_5 function sele ct register p7_5s x0xx x000b 0400dch port p6_6 function select register p6_6s x0xx x000b 0400ddh port p7_6 function select register p7_6s x0xx x000b 0400deh port p6_7 function sele ct register p6_7s x0xx x000b 0400dfh port p7_7 function select register p7_7s x0xx x000b 0400e0h port p8_0 function select register p8_0s x0xx x000b 0400e1h port p9_0 function select register p9_0s x0xx x000b 0400e2h port p8_1 function select register p8_1s x0xx x000b 0400e3h port p9_1 function select register p9_1s x0xx x000b 0400e4h port p8_2 function select register p8_2s x0xx x000b 0400e5h port p9_2 function select register p9_2s x0xx x000b 0400e6h port p8_3 function select register p8_3s x0xx x000b 0400e7h port p9_3 function select register p9_3s 00xx x000b 0400e8h port p8_4 function select register p8_4s xxxx x000b 0400e9h port p9_4 function select register p9_4s 00xx x000b 0400eah 0400ebh port p9_5 function select register p9_5s 00xx x000b 0400ech port p8_6 function se lect register p8_6s xxxx x000b 0400edh port p9_6 function select register p9_6s 00xx x000b 0400eeh port p8_7 function se lect register p8_7s xxxx x000b 0400efh port p9_7 function select register p9_7s x0xx x000b x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 50 of 109 r32c/117 group 4. special function registers (sfrs) table 4.22 sfr list (22) address register symbol reset value 0400f0h port p10_0 function select register p10_0s 0xxx x000b 0400f1h port p11_0 function select register p11_0s x0xx x000b 0400f2h port p10_1 function select register p10_1s 0xxx x000b 0400f3h port p11_1 function select register p11_1s x0xx x000b 0400f4h port p10_2 function select register p10_2s 0xxx x000b 0400f5h port p11_2 function select register p11_2s x0xx x000b 0400f6h port p10_3 function select register p10_3s 0xxx x000b 0400f7h port p11_3 function select register p11_3s x0xx x000b 0400f8h port p10_4 function select register p10_4s 0xxx x000b 0400f9h port p11_4 fu nction select register p11_4s xxxx x000b 0400fah port p10_5 function select register p10_5s 0xxx x000b 0400fbh 0400fch port p10_6 function select register p10_6s 0xxx x000b 0400fdh 0400feh port p10_7 function select register p10_7s 0xxx x000b 0400ffh 040100h port p12_0 function select register p12_0s x0xx x000b 040101h port p13_0 function select register p13_0s xxxx x000b 040102h port p12_1 function select register p12_1s x0xx x000b 040103h port p13_1 function select register p13_1s xxxx x000b 040104h port p12_2 function select register p12_2s x0xx x000b 040105h port p13_2 function select register p13_2s xxxx x000b 040106h port p12_3 function select register p12_3s x0xx x000b 040107h port p13_3 function select register p13_3s xxxx x000b 040108h port p12_4 function select register p12_4s xxxx x000b 040109h port p13_4 function select register p13_4s xxxx x000b 04010ah port p12_5 function select register p12_5s xxxx x000b 04010bh port p13_5 function select register p13_5s xxxx x000b 04010ch port p12_6 function se lect register p12_6s xxxx x000b 04010dh port p13_6 function se lect register p13_6s xxxx x000b 04010eh port p12_7 function select register p12_7s xxxx x000b 04010fh port p13_7 function select register p13_7s xxxx x000b 040110h 040111h port p15_0 function select register p15_0s 00xx x000b 040112h 040113h port p15_1 function select register p15_1s 00xx x000b 040114h 040115h port p15_2 function select register p15_2s 00xx x000b 040116h port p14_3 function se lect register p14_3s xxxx x000b 040117h port p15_3 function select register p15_3s 00xx x000b 040118h port p14_4 function se lect register p14_4s xxxx x000b 040119h port p15_4 function select register p15_4s 00xx x000b 04011ah port p14_5 function se lect register p14_5s xxxx x000b 04011bh port p15_5 function select register p15_5s 00xx x000b 04011ch port p14_6 function se lect register p14_6s xxxx x000b 04011dh port p15_6 function select register p15_6s 00xx x000b 04011eh 04011fh port p15_7 function select register p15_7s 00xx x000b x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 51 of 109 r32c/117 group 4. special function registers (sfrs) table 4.23 sfr list (23) address register symbol reset value 040120h to 04403fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404ah 04404bh 04404ch 04404dh 04404eh watchdog timer start register wdts xxxx xxxxb 04404fh watchdog timer control register wdc 000x xxxxb 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405ah 04405bh 04405ch 04405dh 04405eh 04405fh protect register 2 prcr2 0xxx xxxxb x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 52 of 109 r32c/117 group 4. special function registers (sfrs) table 4.24 sfr list (24) address register symbol reset value 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406ah 04406bh 04406ch 04406dh external interrupt source se lect register 1 ifsr1 x0xx x000b 04406eh 04406fh external interrupt source select register 0 ifsr0 0000 0000b 044070h dma0 request source select register 2 dm0sl2 xx00 0000b 044071h dma1 request source select register 2 dm1sl2 xx00 0000b 044072h dma2 request source select register 2 dm2sl2 xx00 0000b 044073h dma3 request source select register 2 dm3sl2 xx00 0000b 044074h 044075h 044076h 044077h 044078h dma0 request source select register dm0sl xxx0 0000b 044079h dma1 request source select register dm1sl xxx0 0000b 04407ah dma2 request source select register dm2sl xxx0 0000b 04407bh dma3 request source select register dm3sl xxx0 0000b 04407ch 04407dh wake-up ipl setting register 2 ripl2 xx0x 0000b 04407eh 04407fh wake-up ipl setting register 1 ripl1 xx0x 0000b 044080h 044081h 044082h 044083h 044084h 044085h 044086h 044087h 044088h 044089h 04408ah 04408bh 04408ch 04408dh 04408eh 04408fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 53 of 109 r32c/117 group 4. special function registers (sfrs) table 4.25 sfr list (25) address register symbol reset value 044090h to 0443ffh 044400h i 2 c bus transmit/receive shift register i2ctrsr xxh 044401h 044402h i 2 c bus slave address register i2csar 00h 044403h i 2 c bus control register 0 i2ccr0 0000 0000b 044404h i 2 c bus clock control register i2cccr 0000 0000b 044405h i 2 c bus start condition/stop condition control register i2csscr 0000 0000b 044406h i 2 c bus control register 1 i2ccr1 0000 0000b 044407h i 2 c bus control register 2 i2ccr2 0000 0000b 044408h i 2 c bus status register i2csr 0000 0000b 044409h 04440ah 04440bh 04440ch 04440dh 04440eh 04440fh 044410h i 2 c bus mode register i2cmr 0000 0000b 044411h 044412h 044413h 044414h 044415h 044416h 044417h 044418h 044419h 04441ah 04441bh 04441ch 04441dh 04441eh 04441fh 044420h to 0467ffh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 54 of 109 r32c/117 group 4. special function registers (sfrs) table 4.26 sfr list (26) address register symbol reset value 046800h to 047bffh 047c00h can0 mailbox 0: me ssage identifier c0mb0 xxxx xxxxh 047c01h 047c02h 047c03h 047c04h 047c05h can0 mailbox 0: data length xxh 047c06h can0 mailbox 0: data field xxxx xxxx xxxx xxxxh 047c07h 047c08h 047c09h 047c0ah 047c0bh 047c0ch 047c0dh 047c0eh can0 mailbox 0: time stamp xxxxh 047c0fh 047c10h can0 mailbox 1: me ssage identifier c0mb1 xxxx xxxxh 047c11h 047c12h 047c13h 047c14h 047c15h can0 mailbox 1: data length xxh 047c16h can0 mailbox 1: data field xxxx xxxx xxxx xxxxh 047c17h 047c18h 047c19h 047c1ah 047c1bh 047c1ch 047c1dh 047c1eh can0 mailbox 1: time stamp xxxxh 047c1fh 047c20h can0 mailbox 2: me ssage identifier c0mb2 xxxx xxxxh 047c21h 047c22h 047c23h 047c24h 047c25h can0 mailbox 2: data length xxh 047c26h can0 mailbox 2: data field xxxx xxxx xxxx xxxxh 047c27h 047c28h 047c29h 047c2ah 047c2bh 047c2ch 047c2dh 047c2eh can0 mailbox 2: time stamp xxxxh 047c2fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 55 of 109 r32c/117 group 4. special function registers (sfrs) table 4.27 sfr list (27) address register symbol reset value 047c30h can0 mailbox 3: me ssage identifier c0mb3 xxxx xxxxh 047c31h 047c32h 047c33h 047c34h 047c35h can0 mailbox 3: data length xxh 047c36h can0 mailbox 3: data field xxxx xxxx xxxx xxxxh 047c37h 047c38h 047c39h 047c3ah 047c3bh 047c3ch 047c3dh 047c3eh can0 mailbox 3: time stamp xxxxh 047c3fh 047c40h can0 mailbox 4: me ssage identifier c0mb4 xxxx xxxxh 047c41h 047c42h 047c43h 047c44h 047c45h can0 mailbox 4: data length xxh 047c46h can0 mailbox 4: data field xxxx xxxx xxxx xxxxh 047c47h 047c48h 047c49h 047c4ah 047c4bh 047c4ch 047c4dh 047c4eh can0 mailbox 4: time stamp xxxxh 047c4fh 047c50h can0 mailbox 5: me ssage identifier c0mb5 xxxx xxxxh 047c51h 047c52h 047c53h 047c54h 047c55h can0 mailbox 5: data length xxh 047c56h can0 mailbox 5: data field xxxx xxxx xxxx xxxxh 047c57h 047c58h 047c59h 047c5ah 047c5bh 047c5ch 047c5dh 047c5eh can0 mailbox 5: time stamp xxxxh 047c5fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 56 of 109 r32c/117 group 4. special function registers (sfrs) table 4.28 sfr list (28) address register symbol reset value 047c60h can0 mailbox 6: me ssage identifier c0mb6 xxxx xxxxh 047c61h 047c62h 047c63h 047c64h 047c65h can0 mailbox 6: data length xxh 047c66h can0 mailbox 6: data field xxxx xxxx xxxx xxxxh 047c67h 047c68h 047c69h 047c6ah 047c6bh 047c6ch 047c6dh 047c6eh can0 mailbox 6: time stamp xxxxh 047c6fh 047c70h can0 mailbox 7: me ssage identifier c0mb7 xxxx xxxxh 047c71h 047c72h 047c73h 047c74h 047c75h can0 mailbox 7: data length xxh 047c76h can0 mailbox 7: data field xxxx xxxx xxxx xxxxh 047c77h 047c78h 047c79h 047c7ah 047c7bh 047c7ch 047c7dh 047c7eh can0 mailbox 7: time stamp xxxxh 047c7fh 047c80h can0 mailbox 8: me ssage identifier c0mb8 xxxx xxxxh 047c81h 047c82h 047c83h 047c84h 047c85h can0 mailbox 8: data length xxh 047c86h can0 mailbox 8: data field xxxx xxxx xxxx xxxxh 047c87h 047c88h 047c89h 047c8ah 047c8bh 047c8ch 047c8dh 047c8eh can0 mailbox 8: time stamp xxxxh 047c8fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 57 of 109 r32c/117 group 4. special function registers (sfrs) table 4.29 sfr list (29) address register symbol reset value 047c90h can0 mailbox 9: me ssage identifier c0mb9 xxxx xxxxh 047c91h 047c92h 047c93h 047c94h 047c95h can0 mailbox 9: data length xxh 047c96h can0 mailbox 9: data field xxxx xxxx xxxx xxxxh 047c97h 047c98h 047c99h 047c9ah 047c9bh 047c9ch 047c9dh 047c9eh can0 mailbox 9: time stamp xxxxh 047c9fh 047ca0h can0 mailbox 10: message identifier c0mb10 xxxx xxxxh 047ca1h 047ca2h 047ca3h 047ca4h 047ca5h can0 mailbox 10: data length xxh 047ca6h can0 mailbox 10: data field xxxx xxxx xxxx xxxxh 047ca7h 047ca8h 047ca9h 047caah 047cabh 047cach 047cadh 047caeh can0 mailbox 10: time stamp xxxxh 047cafh 047cb0h can0 mailbox 11: message identifier c0mb11 xxxx xxxxh 047cb1h 047cb2h 047cb3h 047cb4h 047cb5h can0 mailbox 11: data length xxh 047cb6h can0 mailbox 11: data field xxxx xxxx xxxx xxxxh 047cb7h 047cb8h 047cb9h 047cbah 047cbbh 047cbch 047cbdh 047cbeh can0 mailbox 11: time stamp xxxxh 047cbfh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 58 of 109 r32c/117 group 4. special function registers (sfrs) table 4.30 sfr list (30) address register symbol reset value 047cc0h can0 mailbox 12: message identifier c0mb12 xxxx xxxxh 047cc1h 047cc2h 047cc3h 047cc4h 047cc5h can0 mailbox 12: data length xxh 047cc6h can0 mailbox 12: data field xxxx xxxx xxxx xxxxh 047cc7h 047cc8h 047cc9h 047ccah 047ccbh 047ccch 047ccdh 047cceh can0 mailbox 12: time stamp xxxxh 047ccfh 047cd0h can0 mailbox 13: message identifier c0mb13 xxxx xxxxh 047cd1h 047cd2h 047cd3h 047cd4h 047cd5h can0 mailbox 13: data length xxh 047cd6h can0 mailbox 13: data field xxxx xxxx xxxx xxxxh 047cd7h 047cd8h 047cd9h 047cdah 047cdbh 047cdch 047cddh 047cdeh can0 mailbox 13: time stamp xxxxh 047cdfh 047ce0h can0 mailbox 14: message identifier c0mb14 xxxx xxxxh 047ce1h 047ce2h 047ce3h 047ce4h 047ce5h can0 mailbox 14: data length xxh 047ce6h can0 mailbox 14: data field xxxx xxxx xxxx xxxxh 047ce7h 047ce8h 047ce9h 047ceah 047cebh 047cech 047cedh 047ceeh can0 mailbox 14: time stamp xxxxh 047cefh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 59 of 109 r32c/117 group 4. special function registers (sfrs) table 4.31 sfr list (31) address register symbol reset value 047cf0h can0 mailbox 15: message identifier c0mb15 xxxx xxxxh 047cf1h 047cf2h 047cf3h 047cf4h 047cf5h can0 mailbox 15: data length xxh 047cf6h can0 mailbox 15: data field xxxx xxxx xxxx xxxxh 047cf7h 047cf8h 047cf9h 047cfah 047cfbh 047cfch 047cfdh 047cfeh can0 mailbox 15: time stamp xxxxh 047cffh 047d00h can0 mailbox 16: message identifier c0mb16 xxxx xxxxh 047d01h 047d02h 047d03h 047d04h 047d05h can0 mailbox 16: data length xxh 047d06h can0 mailbox 16: data field xxxx xxxx xxxx xxxxh 047d07h 047d08h 047d09h 047d0ah 047d0bh 047d0ch 047d0dh 047d0eh can0 mailbox 16: time stamp xxxxh 047d0fh 047d10h can0 mailbox 17: message identifier c0mb17 xxxx xxxxh 047d11h 047d12h 047d13h 047d14h 047d15h can0 mailbox 17: data length xxh 047d16h can0 mailbox 17: data field xxxx xxxx xxxx xxxxh 047d17h 047d18h 047d19h 047d1ah 047d1bh 047d1ch 047d1dh 047d1eh can0 mailbox 17: time stamp xxxxh 047d1fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 60 of 109 r32c/117 group 4. special function registers (sfrs) table 4.32 sfr list (32) address register symbol reset value 047d20h can0 mailbox 18: message identifier c0mb18 xxxx xxxxh 047d21h 047d22h 047d23h 047d24h 047d25h can0 mailbox 18: data length xxh 047d26h can0 mailbox 18: data field xxxx xxxx xxxx xxxxh 047d27h 047d28h 047d29h 047d2ah 047d2bh 047d2ch 047d2dh 047d2eh can0 mailbox 18: time stamp xxxxh 047d2fh 047d30h can0 mailbox 19: message identifier c0mb19 xxxx xxxxh 047d31h 047d32h 047d33h 047d34h 047d35h can0 mailbox 19: data length xxh 047d36h can0 mailbox 19: data field xxxx xxxx xxxx xxxxh 047d37h 047d38h 047d39h 047d3ah 047d3bh 047d3ch 047d3dh 047d3eh can0 mailbox 19: time stamp xxxxh 047d3fh 047d40h can0 mailbox 20: message identifier c0mb20 xxxx xxxxh 047d41h 047d42h 047d43h 047d44h 047d45h can0 mailbox 20: data length xxh 047d46h can0 mailbox 20: data field xxxx xxxx xxxx xxxxh 047d47h 047d48h 047d49h 047d4ah 047d4bh 047d4ch 047d4dh 047d4eh can0 mailbox 20: time stamp xxxxh 047d4fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 61 of 109 r32c/117 group 4. special function registers (sfrs) table 4.33 sfr list (33) address register symbol reset value 047d50h can0 mailbox 21: message identifier c0mb21 xxxx xxxxh 047d51h 047d52h 047d53h 047d54h 047d55h can0 mailbox 21: data length xxh 047d56h can0 mailbox 21: data field xxxx xxxx xxxx xxxxh 047d57h 047d58h 047d59h 047d5ah 047d5bh 047d5ch 047d5dh 047d5eh can0 mailbox 21: time stamp xxxxh 047d5fh 047d60h can0 mailbox 22: message identifier c0mb22 xxxx xxxxh 047d61h 047d62h 047d63h 047d64h 047d65h can0 mailbox 22: data length xxh 047d66h can0 mailbox 22: data field xxxx xxxx xxxx xxxxh 047d67h 047d68h 047d69h 047d6ah 047d6bh 047d6ch 047d6dh 047d6eh can0 mailbox 22: time stamp xxxxh 047d6fh 047d70h can0 mailbox 23: message identifier c0mb23 xxxx xxxxh 047d71h 047d72h 047d73h 047d74h 047d75h can0 mailbox 23: data length xxh 047d76h can0 mailbox 23: data field xxxx xxxx xxxx xxxxh 047d77h 047d78h 047d79h 047d7ah 047d7bh 047d7ch 047d7dh 047d7eh can0 mailbox 23: time stamp xxxxh 047d7fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 62 of 109 r32c/117 group 4. special function registers (sfrs) table 4.34 sfr list (34) address register symbol reset value 047d80h can0 mailbox 24: message identifier c0mb24 xxxx xxxxh 047d81h 047d82h 047d83h 047d84h 047d85h can0 mailbox 24: data length xxh 047d86h can0 mailbox 24: data field xxxx xxxx xxxx xxxxh 047d87h 047d88h 047d89h 047d8ah 047d8bh 047d8ch 047d8dh 047d8eh can0 mailbox 24: time stamp xxxxh 047d8fh 047d90h can0 mailbox 25: message identifier c0mb25 xxxx xxxxh 047d91h 047d92h 047d93h 047d94h 047d95h can0 mailbox 25: data length xxh 047d96h can0 mailbox 25: data field xxxx xxxx xxxx xxxxh 047d97h 047d98h 047d99h 047d9ah 047d9bh 047d9ch 047d9dh 047d9eh can0 mailbox 25: time stamp xxxxh 047d9fh 047da0h can0 mailbox 26: message identifier c0mb26 xxxx xxxxh 047da1h 047da2h 047da3h 047da4h 047da5h can0 mailbox 26: data length xxh 047da6h can0 mailbox 26: data field xxxx xxxx xxxx xxxxh 047da7h 047da8h 047da9h 047daah 047dabh 047dach 047dadh 047daeh can0 mailbox 26: time stamp xxxxh 047dafh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 63 of 109 r32c/117 group 4. special function registers (sfrs) table 4.35 sfr list (35) address register symbol reset value 047db0h can0 mailbox 27: message identifier c0mb27 xxxx xxxxh 047db1h 047db2h 047db3h 047db4h 047db5h can0 mailbox 27: data length xxh 047db6h can0 mailbox 27: data field xxxx xxxx xxxx xxxxh 047db7h 047db8h 047db9h 047dbah 047dbbh 047dbch 047dbdh 047dbeh can0 mailbox 27: time stamp xxxxh 047dbfh 047dc0h can0 mailbox 28: message identifier c0mb28 xxxx xxxxh 047dc1h 047dc2h 047dc3h 047dc4h 047dc5h can0 mailbox 28: data length xxh 047dc6h can0 mailbox 28: data field xxxx xxxx xxxx xxxxh 047dc7h 047dc8h 047dc9h 047dcah 047dcbh 047dcch 047dcdh 047dceh can0 mailbox 28: time stamp xxxxh 047dcfh 047dd0h can0 mailbox 29: message identifier c0mb29 xxxx xxxxh 047dd1h 047dd2h 047dd3h 047dd4h 047dd5h can0 mailbox 29: data length xxh 047dd6h can0 mailbox 29: data field xxxx xxxx xxxx xxxxh 047dd7h 047dd8h 047dd9h 047ddah 047ddbh 047ddch 047dddh 047ddeh can0 mailbox 29: time stamp xxxxh 047ddfh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 64 of 109 r32c/117 group 4. special function registers (sfrs) table 4.36 sfr list (36) address register symbol reset value 047de0h can0 mailbox 30: message identifier c0mb30 xxxx xxxxh 047de1h 047de2h 047de3h 047de4h 047de5h can0 mailbox 30: data length xxh 047de6h can0 mailbox 30: data field xxxx xxxx xxxx xxxxh 047de7h 047de8h 047de9h 047deah 047debh 047dech 047dedh 047deeh can0 mailbox 30: time stamp xxxxh 047defh 047df0h can0 mailbox 31: message identifier c0mb31 xxxx xxxxh 047df1h 047df2h 047df3h 047df4h 047df5h can0 mailbox 31: data length xxh 047df6h can0 mailbox 31: data field xxxx xxxx xxxx xxxxh 047df7h 047df8h 047df9h 047dfah 047dfbh 047dfch 047dfdh 047dfeh can0 mailbox 31: time stamp xxxxh 047dffh 047e00h can0 acceptance mask register 0 c0mkr0 xxxx xxxxh 047e01h 047e02h 047e03h 047e04h can0 acceptance mask register 1 c0mkr1 xxxx xxxxh 047e05h 047e06h 047e07h 047e08h can0 acceptance mask register 2 c0mkr2 xxxx xxxxh 047e09h 047e0ah 047e0bh 047e0ch can0 acceptance mask register 3 c0mkr3 xxxx xxxxh 047e0dh 047e0eh 047e0fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 65 of 109 r32c/117 group 4. special function registers (sfrs) table 4.37 sfr list (37) address register symbol reset value 047e10h can0 acceptance mask register 4 c0mkr4 xxxx xxxxh 047e11h 047e12h 047e13h 047e14h can0 acceptance mask register 5 c0mkr5 xxxx xxxxh 047e15h 047e16h 047e17h 047e18h can0 acceptance mask register 6 c0mkr6 xxxx xxxxh 047e19h 047e1ah 047e1bh 047e1ch can0 acceptance mask register 7 c0mkr7 xxxx xxxxh 047e1dh 047e1eh 047e1fh 047e20h can0 fifo receive id compare register 0 c0fidcr0 xxxx xxxxh 047e21h 047e22h 047e23h 047e24h can0 fifo receive id compare register 1 c0fidcr1 xxxx xxxxh 047e25h 047e26h 047e27h 047e28h can0 mask invalid register c0mkivlr xxxx xxxxh 047e29h 047e2ah 047e2bh 047e2ch can0 mailbox interrupt enable register c0mier xxxx xxxxh 047e2dh 047e2eh 047e2fh 047e30h 047e31h 047e32h 047e33h 047e34h 047e35h 047e36h 047e37h 047e38h 047e39h 047e3ah 047e3bh 047e3ch 047e3dh 047e3eh 047e3fh 047e40h to 047f1fh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 66 of 109 r32c/117 group 4. special function registers (sfrs) table 4.38 sfr list (38) address register symbol reset value 047f20h can0 message control register 0 c0mctl0 00h 047f21h can0 message control register 1 c0mctl1 00h 047f22h can0 message control register 2 c0mctl2 00h 047f23h can0 message control register 3 c0mctl3 00h 047f24h can0 message control register 4 c0mctl4 00h 047f25h can0 message control register 5 c0mctl5 00h 047f26h can0 message control register 6 c0mctl6 00h 047f27h can0 message control register 7 c0mctl7 00h 047f28h can0 message control register 8 c0mctl8 00h 047f29h can0 message control register 9 c0mctl9 00h 047f2ah can0 message control register 10 c0mctl10 00h 047f2bh can0 message control register 11 c0mctl11 00h 047f2ch can0 message control register 12 c0mctl12 00h 047f2dh can0 message control register 13 c0mctl13 00h 047f2eh can0 message control register 14 c0mctl14 00h 047f2fh can0 message control register 15 c0mctl15 00h 047f30h can0 message control register 16 c0mctl16 00h 047f31h can0 message control register 17 c0mctl17 00h 047f32h can0 message control register 18 c0mctl18 00h 047f33h can0 message control register 19 c0mctl19 00h 047f34h can0 message control register 20 c0mctl20 00h 047f35h can0 message control register 21 c0mctl21 00h 047f36h can0 message control register 22 c0mctl22 00h 047f37h can0 message control register 23 c0mctl23 00h 047f38h can0 message control register 24 c0mctl24 00h 047f39h can0 message control register 25 c0mctl25 00h 047f3ah can0 message control register 26 c0mctl26 00h 047f3bh can0 message control register 27 c0mctl27 00h 047f3ch can0 message control register 28 c0mctl28 00h 047f3dh can0 message control register 29 c0mctl29 00h 047f3eh can0 message control register 30 c0mctl30 00h 047f3fh can0 message control register 31 c0mctl31 00h x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 67 of 109 r32c/117 group 4. special function registers (sfrs) table 4.39 sfr list (39) address register symbol reset value 047f40h can0 control register c0ctlr 0000 0101b 047f41h 0000 0000b 047f42h can0 status register c0str 0000 0101b 047f43h 0000 0000b 047f44h can0 bit configuration register c0bcr 00 0000h 047f45h 047f46h 047f47h can0 clock select register c0clkr 000x 0000b 047f48h can0 receive fifo control register c0rfcr 1000 0000b 047f49h can0 receive fifo pointer control register c0rfpcr xxh 047f4ah can0 transmit fifo c ontrol register c0tfcr 1000 0000b 047f4bh can0 transmit fifo pointer control register c0tfpcr xxh 047f4ch can0 error interrupt enable register c0eier 00h 047f4dh can0 error interrupt factor judge register c0eifr 00h 047f4eh can0 reception error count register c0recr 00h 047f4fh can0 transmission error count register c0tecr 00h 047f50h can0 error code store register c0ecsr 00h 047f51h can0 channel search support register c0cssr xxh 047f52h can0 mailbox search status register c0mssr 1000 0000b 047f53h can0 mailbox search mode register c0msmr xxxx xx00b 047f54h can0 time stamp register c0tsr 0000h 047f55h 047f56h can0 acceptance filter support register c0afsr xxxxh 047f57h 047f58h can0 test control register c0tcr 00h 047f59h 047f5ah 047f5bh 047f5ch 047f5dh 047f5eh 047f5fh 047f60h to 047fffh 048000h to 04ffffh x: undefined blanks are reserved. no access is allowed.
rej03b0254-0101 rev.1.01 mar 11, 2010 page 68 of 109 r32c/117 group 5. electrical characteristics 5. electrical characteristics notes: 1. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect device reliability. 2. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. port p9_1 is designated as input pin in the 100-pin package. table 5.1 absolute maximum ratings (1) symbol characteristic condition value unit v cc supply voltage v cc = av cc -0.3 to 6.0 v av cc analog supply voltage v cc = av cc -0.3 to 6.0 v v i input voltage xin, reset , cnvss, nsd, v ref , p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p5_0 to p5_3, p8_4 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0top11_4, p12_0top12_7, p13_0 to p13_7, p14_1, p14_3 to p14_6, p15_0 to p15_7 (2) -0.3 to v cc + 0.3 v p4_0 to p4_7, p5_4 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_3 -0.3 to 6.0 v v o output voltage xout, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0top11_4, p12_0top12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (2) -0.3 to v cc + 0.3 v p d power consumption t a = 25c 500 mw ? operating temperature range -40 to 85 c t stg storage temperature range -65 to 150 c
rej03b0254-0101 rev.1.01 mar 11, 2010 page 69 of 109 r32c/117 group 5. electrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. v ih and v il for p8_7 are specified for p8_7 as a programmable port. these values are not applicable to p8_7 as xcin. 3. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. port p9_1 is designated as input pin in the 100-pin package. table 5.2 operating conditions (1/5) (1) symbol characteristic value unit min. typ. max. v cc digital supply voltage 3.0 5.0 5.5 v av cc analog supply voltage v cc v v ref reference voltage 3.0 v cc v v ss digital ground voltage 0v av ss analog ground voltage 0v dv cc /dt v cc ramp up rate (v cc < 2.0 v) 0.05 v/ms v ih high level input voltage xin, reset , cnvss, nsd, p2_0 to p2_7, p3_0 to p3_7, p5_0 to p5_3, p8_4 to p8_7 (2) , p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p14_1, p14_3 to p14_6, p15_0 to p15_7 (3) 0.8 v cc v cc v p4_0 to p4_7, p5_4 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_3 0.8 v cc 6.0 v p0_0 to p0_7, p1_0 to p1_7, p12_0 to p12_7, p13_0 to p13_7 (3) in single-chip mode 0.8 v cc v cc v in memory expansion mode or microprocessor mode 0.5 v cc v cc v v il low level input voltage xin, reset , cnvss, nsd, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7 (2) , p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p14_1, p14_3 to p14_6, p15_0 to p15_7 (3) 0 0.2 v cc v p0_0 to p0_7, p1_0 to p1_7, p12_0 to p12_7, p13_0 to p13_7 (3) in single-chip mode 0 0.2 v cc v in memory expansion mode or microprocessor mode 0 0.16 v cc v t opr operating temperature range version n -20 85 c version d -40 85 c version p -40 85 c
rej03b0254-0101 rev.1.01 mar 11, 2010 page 70 of 109 r32c/117 group 5. electrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. this value should be satisfied with due consid eration of every condition as follows: operating temperature, dc bias, aging, etc. table 5.3 operating conditions (2/5) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value (2) unit min. typ. max. c vdc decoupling capacitance for voltage regulator inter-pin voltage: 1.5 v 2.4 10.0 f
rej03b0254-0101 rev.1.01 mar 11, 2010 page 71 of 109 r32c/117 group 5. electrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. the following conditions should be satisfied: ? the sum of i ol(peak) of ports p0, p1, p2, p8_6, p8_7, p9, p10, p11, p14, and p15 is 80 ma or less. ? the sum of i ol(peak) of ports p3, p4, p5, p6, p7, p8_0 to p8 _4, p12, and p13 is 80 ma or less. ? the sum of i oh(peak) of ports p0, p1, p2, and p11 is -40 ma or less. ? the sum of i oh(peak) of ports p8_6, p8_7, p9, p10, p14, and p15 is -40 ma or less. ? the sum of i oh(peak) of ports p3, p4, p5, p12, and p13 is -40 ma or less. ? the sum of i oh(peak) of ports p6, p7, and p8_0 to p8_4 is -40 ma or less. 3. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. port p9_1 is designated as input pin in the 100-pin package. 4. average value within 100 ms. table 5.4 operating conditions (3/5) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. i oh (peak) high level peak output current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (3) -10.0 ma i oh (avg) high level average output current (4) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (3) -5.0 ma i ol (peak) low level peak output current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (3) 10.0 ma i ol (avg) low level average output current (4) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (3) 5.0 ma
rej03b0254-0101 rev.1.01 mar 11, 2010 page 72 of 109 r32c/117 group 5. electrical characteristics note: 1. the device is operationally guaranteed under these operating conditions. figure 5.1 clock cycle time table 5.5 operating conditions (4/5) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. f (xin) main clock osc illator frequency 416mhz f (xref) reference clock frequency 24mhz f (pll) pll clock oscilla tor frequency 96 128 mhz f (base) base clock frequency 50 mhz t c(base) base clock cycle time 20 ns f (cpu) cpu operating frequency 50 mhz t c (cpu) cpu clock cycle time 20 ns f (bclk) peripheral bus clock operating frequency 25 mhz t c (bclk) peripheral bus clock cycle time 40 ns f (per) peripheral clock source frequency 32 mhz f (xcin) sub clock oscillator frequency 32.768 62.5 khz base clock (internal signal) t c(base) peripheral bus clock (internal signal) t c(bclk) cpu clock (internal signal) t c(cpu)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 73 of 109 r32c/117 group 5. electrical characteristics note: 1. the device is operationally guaranteed under these operating conditions. figure 5.2 ripple waveform table 5.6 operating conditions (5/5) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. v r(vcc) allowable ripple voltage v cc = 5.0 v 0.5 vp-p v cc = 3.0 v 0.3 vp-p dv r(vcc) /dt ripple voltage gradient v cc = 5.0 v 0.3 v/ms v cc = 3.0 v 0.3 v/ms f r(vcc) allowable ripple frequency 10 khz v cc 1 / f r(vcc) v r(vcc)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 74 of 109 r32c/117 group 5. electr ical characteristics notes: 1. program/erase definition this value represents the number of erasures per block. if the flash memory is programmed/erased n times, each block can be erased n times. i.e. if 4-word write is performed in 512 different addresses in the block a of 4 kbyte and then the block is erased, it is considered the pr ogramming/erasure is performed just once. however a write in the same address more than once for one erasure is disabled. (overwrite disabled). 2. the data retention time includes the periods when the supply voltage is not applied and no clock is provided. 3. please contact a renesas sales office regard ing data retention time other than the above. table 5.7 ram electrical characteristics (v cc = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v rdr ram data retention voltage in stop mode 2.0 v table 5.8 flash memory electrical characteristics (v cc = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic value unit min. typ. max. ? programming and erasure endurance of flash memory (1) program area 1000 times data area 10000 times ? 4-word program time program area 150 900 s data area 300 1700 s ? lock bit-program time program area 70 500 s data area 140 1000 s ? block erasure time 4 kbyte block 0.12 3.0 s 32 kbyte block 0.17 3.0 s 64 kbyte block 0.20 3.0 s ? data retention (2) t a = 55c (3) 10 years
rej03b0254-0101 rev.1.01 mar 11, 2010 page 75 of 109 r32c/117 group 5. electr ical characteristics figure 5.3 power supply circuit timing table 5.9 power supply circ uit timing characteristics (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. t d(p-r) internal power supply start-up stabilization time after the main power supply is turned on 2ms table 5.10 electrical charac teristics of voltage regu lator for internal logic (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. v vdc1 output voltage 1.5 v table 5.11 electrical characteri stics of low voltage detector (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. vdet detected voltage error 0.3 v vdet(r)-vdet(f) hysteresis width 0 v ? self-consuming current v cc = 5.0 v, low voltage detector enabled 4a t d(e-a) operation start time of low voltage detector 150 s t d(p-r) v cc pll oscillator- output waveform internal power supply start-up stabilization time after the main power supply is turned on recommended operating voltage t d(p-r) supply voltage for internal logic
rej03b0254-0101 rev.1.01 mar 11, 2010 page 76 of 109 r32c/117 group 5. electr ical characteristics note: 1. this value is applicable only when the main clock osc illation is stable. note: 1. this recovery time does not in clude the period until the main cl ock oscillator is stabilized. the cpu starts operating before th e oscillator is stabilized. figure 5.4 clock circuit timing table 5.12 electrical char acteristics of oscillator (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. f so(pll) pll clock self-osc illation frequency 35 50 65 mhz t lock(pll) pll lock time (1) 1ms t jitter(p-p) pll jitter period (p-p) 2.0 ns f (oco) on-chip oscillator frequency 62.5 125 250 khz table 5.13 electrical characte ristics of clock circuitry (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. t rec(wait) recovery time from wait mode to low power mode 225 s t rec(stop) recovery time from stop mode (1) 225 s t rec(stop) interrupt for exiting stop mode cpu clock main clock oscillator output on-chip oscillator output sub clock oscillator output on-chip oscillator output t rec(wait) interrupt for exiting wait mode cpu clock recovery time from stop mode t rec(stop) recovery time from wait mode to low power mode t rec(wait)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 77 of 109 r32c/117 group 5. electr ical characteristics timing requirements (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) figure 5.5 flash memory cpu rewrite mode timing table 5.14 flash memory cpu rewrite mode timing symbol characteristics value unit min. max. t cr read cycle time 200 ns t su(s-r) chip-select setup time for read 200 ns t h(r-s) chip-select hold time after read 0ns t su(a-r) address setup time for read 200 ns t h(r-a) address hold time after read 0ns t w(r) read pulse width 100 ns t cw write cycle time 200 ns t su(s-w) chip-select setup time for write 0ns t h(w-s) chip-select hold time after write 30 ns t su(a-w) address setup time for write 0ns t h(w-a) address hold time after write 30 ns t w(w) write pulse width 50 ns cs0 a23 to a0, bc0 to bc3 rd t h(r-s) read cycle t w(r) t su(s-r) t h(r-a) t su(a-r) write cycle cs0 to cs3 a23 to a0, bc0 to bc3 wr t h(w-s) t w(w) t su(s-w) t h(w-a) t su(a-w) t cw t cr
rej03b0254-0101 rev.1.01 mar 11, 2010 page 78 of 109 r32c/117 group 5. electrical characteristics v cc =5v note: 1. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. port p9_1 is designated as input pin in the 100-pin package. table 5.15 electrical characteristics (1/3) (v cc = 4.2 to 5.5 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v oh high level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0top10_7, p11_0top11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (1) i oh = -5 ma v cc - 2.0 v cc v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0top10_7, p11_0top11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (1) i oh = -200 a v cc - 0.3 v cc v v ol low level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0top10_7, p11_0top11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (1) i ol = 5 ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0top10_7, p11_0top11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (1) i ol = 200 a 0.45 v
rej03b0254-0101 rev.1.01 mar 11, 2010 page 79 of 109 r32c/117 group 5. electrical characteristics v cc =5v notes: 1. pins int6 to int8 are available in the 144-pin package only. 2. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. port p9_1 is designated as input pin in the 100-pin package. table 5.16 electrical ch aracteristics (2/3) (v cc = 4.2 to 5.5 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v t+ - v t- hysteresis hold , rdy , nmi , int0 to int8 , ki0 to ki3 , ta0in to ta4in, ta0out to ta4out, tb0in to tb5in, cts0 to cts8 , clk0 to clk8, rxd0 to rxd8, scl0 to scl6, sda0 to sda6, ss0 to ss6 , srxd0tosrxd6, adtrg , iio0_0 to iio0_7, iio1_0 to iio1_7, ud0a, ud0b, ud1a, ud1b, isclk2, isrxd2, iein, can0in, can0wu (1) 0.2 1.0 v reset 0.2 1.8 v i ih high level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0top11_4, p12_0top12_7, p13_0 to p13_7, p14_1, p14_3 to p14_6, p15_0top15_7 (2) v i = 5 v 5.0 a i il low level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0top11_4, p12_0top12_7, p13_0 to p13_7, p14_1, p14_3 to p14_6, p15_0top15_7 (2) v i = 0 v -5.0 a r pullup pull-up resistor p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p5_0 to p5_3, p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0top11_4, p12_0top12_7, p13_0 to p13_7, p14_1, p14_3 to p14_6, p15_0top15_7 (2) v i = 0 v 30 50 170 k r f xin feedback resistor xin 1.5 m r f xcin feedback resistor xcin 15 m
rej03b0254-0101 rev.1.01 mar 11, 2010 page 80 of 109 r32c/117 group 5. electrical characteristics v cc =5v table 5.17 electrical characteristics (3/3) (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characte ristic measurement condition value unit min. typ. max. i cc power supply current in single-chip mode, output pins are left open and others are connected to v ss xin-xout drive power: low xcin-xcout drive power: low f (cpu) =50mhz, f (bclk) =25mhz, f (xin) =8mhz, active: xin, pll, stopped: xcin, oco 35 50 ma f (cpu) = f so(pll) /24 mhz, active: pll (self-oscillation), stopped: xin, xcin, oco 12 ma f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco 1.2 ma f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown 220 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown 230 a f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco, t a = 25c, wait mode 960 1600 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown, t a = 25c, wait mode 8140a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown, t a = 25c, wait mode 10 150 a stopped: all clocks, main regulator: shutdown, t a = 25c 570a
rej03b0254-0101 rev.1.01 mar 11, 2010 page 81 of 109 r32c/117 group 5. electrical characteristics v cc =5v note: 1. pins an15_0 to an15_7 are available in the 144-pin package only. table 5.18 a/d conversion characteristics (v cc =av cc =v ref =4.2to5.5v, v ss =av ss =0v, t a =t opr , and f (bclk) = 25 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution v ref = v cc 10 bits ? absolute error v ref = v cc = 5 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, an15_0 to an15_7, anex0, anex1 (1) 3 lsb external op-amp connection mode 7 lsb inl integral non-linearity error v ref = v cc = 5 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, an15_0 to an15_7, anex0, anex1 (1) 3 lsb external op-amp connection mode 7 lsb dnl differential non-linearity error 1 lsb ?offset error 3 lsb ? gain error 3 lsb r ladder resistor ladder v ref = v cc 420k t conv conversion time (10 bits) ad = 16 mhz, with sample and hold function 2.06 s ad = 16 mhz, without sample and hold function 3.69 s t conv conversion time (8 bits) ad = 16 mhz, with sample and hold function 1.75 s ad = 16 mhz, without sample and hold function 3.06 s t samp sampling time ad = 16 mhz 0.188 s v ia analog input voltage 0 v ref v ad operating clock frequency without sample and hold function 0.25 16 mhz with sample and hold function 1 16 mhz
rej03b0254-0101 rev.1.01 mar 11, 2010 page 82 of 109 r32c/117 group 5. electrical characteristics v cc =5v note: 1. one d/a converter is used. the dai register (i = 0, 1) of the other unused converter is set to 00h. the resistor ladder for a/d converter is not considered. even when the vcut bit in the ad0con1 register is set to 0 (v ref disconnected), i vref is supplied. table 5.19 d/a conversion characteristics (v cc =av cc =v ref =4.2to5.5v, v ss =av ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution 8bits ? absolute precision 1.0 % t s settling time 3s r o output resistance 41020k i vref reference input current (1) 1.5 ma
rej03b0254-0101 rev.1.01 mar 11, 2010 page 83 of 109 r32c/117 group 5. electrical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.20 external clock input symbol characteristic value unit min. max. t c (x) external clock input period 62.5 250 ns t w(xh) external clock input high level pulse width 25 ns t w(xl) external clock input low level pulse width 25 ns t r (x) external clock input rise time 5ns t f (x) external clock input fall time 5ns t w / t c external clock input duty 40 60 % table 5.21 external bus timing symbol characteristic value unit min. max. t su (d-r) data setup time for read 40 ns t h (r-d) data hold time after read 0ns t dis (r-d) data disable time after read 0.5 t c(base) + 10 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 84 of 109 r32c/117 group 5. electrical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.22 timer a input (counti ng input in event counter mode) symbol characteristic value unit min. max. t c (ta) taiin input clock period 200 ns t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.23 timer a input (gating input in timer mode) symbol characteristic value unit min. max. t c (ta) taiin input clock period 400 ns t w (tah) taiin input high level pulse width 180 ns t w (tal) taiin input low level pulse width 180 ns table 5.24 timer a input (external trigger input in one-shot timer mode) symbol characteristic value unit min. max. t c (ta) taiin input clock period 200 ns t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.25 timer a input (external trigge r input in pulse-width modulation mode) symbol characteristic value unit min. max. t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.26 timer a input (increment/decrement count switching input in event counter mode) symbol characteristic value unit min. max. t c (up) taiout input clock period 2000 ns t w (uph) taiout input high level pulse width 1000 ns t w (upl) taiout input low level pulse width 1000 ns t su (up-tin) taiout input setup time 400 ns t h (tin-up) taiout input hold time 400 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 85 of 109 r32c/117 group 5. electrical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.27 timer b input (counti ng input in event counter mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock period (one edge counting) 200 ns t w (tbh) tbiin input high level pulse width (one edge counting) 80 ns t w (tbl) tbiin input low level pulse width (one edge counting) 80 ns t c (tb) tbiin input clock period (both edges counting) 200 ns t w (tbh) tbiin input high level pulse width (both edges counting) 80 ns t w (tbl) tbiin input low level pulse width (both edges counting) 80 ns table 5.28 timer b input (pulse period measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock period 400 ns t w (tbh) tbiin input high level pulse width 180 ns t w (tbl) tbiin input low level pulse width 180 ns table 5.29 timer b input (pulse-width measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock period 400 ns t w (tbh) tbiin input high level pulse width 180 ns t w (tbl) tbiin input low level pulse width 180 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 86 of 109 r32c/117 group 5. electrical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.30 serial interface symbol characteristic value unit min. max. t c (ck) clki input clock period 200 ns t w (ckh) clki input high level pulse width 80 ns t w (ckl) clki input low level pulse width 80 ns t su (d-c) rxdi input setup time 80 ns t h (c-d) rxdi input hold time 90 ns table 5.31 a/d trigger input symbol characteristic value unit min. max. t w (adh) adtrg input high level pulse width hardware trigger input high level pulse width ns t w (adl) adtrg input low level pulse width hardware trigger input high level pulse width 125 ns table 5.32 external interrupt inti input symbol characteristic value unit min. max. t w (inh) inti input high level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns t w (inl) inti input low level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns table 5.33 intelligent i/o symbol characteristic value unit min. max. t c(isclk2) isclk2 input clock period 600 ns t w(isclk2h) isclk2 input high level pulse width 270 ns t w(isclk2l) isclk2 input low level pulse width 270 ns t su(rxd-isclk2) isrxd2 input setup time 150 ns t h(isclk2-rxd) isrxd2 input hold time 100 ns 3 ad --------- -
rej03b0254-0101 rev.1.01 mar 11, 2010 page 87 of 109 r32c/117 group 5. electrical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated by the following formulas based on a value ssc set by bits ssc4 to ssc0 in the i2csscr register: t h(sda-scl)s = ssc 2 t c( iic) + 40 [ns] t su(scl-sda)p = (ssc 2 + 1) t c( iic) + 40 [ns] t w(sdah)p = (ssc + 1) t c( iic) + 40 [ns] table 5.34 multi-master i 2 c-bus interface symbol characteristic value unit standard-mode fast-mode min. max. min. max. t w(sclh) mscl input high level pulse width 600 600 ns t w(scll) mscl input low level pulse width 600 600 ns t r(scl) mscl input rise time 1000 300 ns t f(scl) mscl input fall time 300 300 ns t r(sda) msda input rise time 1000 300 ns t f(sda) msda input fall time 300 300 ns t h(sda-scl)s mscl high level hold time after start condition/restart condition (1) 2 t c( iic) + 40 ns t su(scl-sda)p mscl high level setup time for restart condition/stop condition (1) 2 t c( iic) + 40 ns t w(sdah)p msda high level pulse width after stop condition (1) 4 t c( iic) + 40 ns t su(sda-scl) msda input setup time 100 100 ns t h(scl-sda) msda input hold time 00ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 88 of 109 r32c/117 group 5. electrical characteristics v cc =5v switching characteristics (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated by the following formulas based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative valu e, modify the value to be set. fo r the details of how to set values, refer to the hardware manual. t su(s-r) = t su(a-r) = tsu(a-r) t c(base) - 15 [ns] t w(r) = tw(r) t c(base) - 10 [ns] t su(s-w) = t su(a-w) = tsu(a-w) t c(base) - 15 [ns] t w(w) = t su(d-w) = tw(w) t c(base) - 10 [ns] table 5.35 external bus timing (separate bus) symbol characteristic measurement condition value unit min. max. t su (s-r) chip-select setup time for read refer to figure 5.6 (1) ns t h (r-s) chip-select hold time after read t c(base) - 15 ns t su (a-r) address setup time for read (1) ns t h (r-a) address hold time after read t c(base) - 15 ns t w (r) read pulse width (1) ns t su (s-w) chip-select setup time for write (1) ns t h (w-s) chip-select hold time after write 1.5 t c(base) - 15 ns t su (a-w) address setup time for write (1) ns t h (w-a) address hold time after write 1.5 t c(base) - 15 ns t w (w) write pulse width (1) ns t su (d-w) data setup time for write (1) ns t h (w-d) data hold time after write 0ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 89 of 109 r32c/117 group 5. electrical characteristics v cc =5v switching characteristics (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated by the following formulas based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative valu e, modify the value to be set. fo r the details of how to set values, refer to the hardware manual. t su(s-ale) = t su(a-ale) = t w(ale) = (tsu(a-r) - 0.5) t c(base) -15 [ns] t w(r) = tw(r) t c(base) -10 [ns] t w(w) = t su(d-w) = tw(w) t c(base) -10 [ns] table 5.36 external bus timing (multiplexed bus) symbol characteristic measurement condition value unit min. max. t su (s-ale) chip-select setup time for ale refer to figure 5.6 (1) ns t h(r-s) chip-select hold time after read 1.5 t c(base) - 15 ns t su(a-ale) address setup time for ale (1) ns t h(ale-a) address hold time after ale 0.5 t c(base) - 5 ns t h(r-a) address hold time after read 1.5 t c(base) - 15 ns t d(ale-r) ale-read delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w(ale) ale pulse width (1) ns t dis(r-a) address disable time after read 8ns t w(r) read pulse width (1) ns t h(w-s) chip-select hold time after write 1.5 t c(base) - 15 ns t h(w-a) address hold time after write 1.5 t c(base) - 15 ns t d(ale-w) ale-write delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w(w) write pulse width (1) ns t su(d-w) data setup time for write (1) ns t h(w-d) data hold time after write 0.5 t c(base) ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 90 of 109 r32c/117 group 5. electrical characteristics v cc =5v switching characteristics (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. external circuits are required to satisfy the i 2 c-bus specification. table 5.37 serial interface symbol characteristic measurement condition value unit min. max. t d (c-q) txdi output delay time refer to figure 5.6 80 ns t h (c-q) txdi output hold time 0ns table 5.38 intelligent i/o symbol characteristic measurement condition value unit min. max. t d (isclk2-txd) istxd2 output delay time refer to figure 5.6 180 ns t h (isclk2-rxd) istxd2 output hold time 0ns table 5.39 multi-master i 2 c-bus interface (standard-mode) symbol characteristic measurement condition value unit min. max. t f(scl) mscl output fall time refer to figure 5.6 2ns t f(sda) msda output fall time 2ns t d(sda-scl)s mscl output delay time after start condition/restart condition 20 t c( iic) - 120 52 t c( iic) - 40 ns t d(scl-sda)p restart condition/stop condition output delay time after mscl becomes high 20 t c( iic) + 40 52 t c( iic) + 120 ns t d(scl-sda) msda output delay time 2 t c( iic) + 40 3 t c( iic) + 120 ns table 5.40 multi-master i 2 c-bus interface (fast-mode) symbol characteristic measurement condition value unit min. max. t f(scl) mscl output fall time refer to figure 5.6 2 (1) ns t f(sda) msda output fall time 2 (1) ns t d(sda-scl)s mscl output delay time after start condition/restart condition 10 t c( iic) - 120 26 t c( iic) - 40 ns t d(scl-sda)p restart condition/stop condition output delay time after mscl becomes high 10 t c( iic) + 40 26 t c( iic) + 120 ns t d(scl-sda) msda output delay time 2 t c( iic) + 40 3 t c( iic) + 120 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 91 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v note: 1. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. port p9_1 is designated as input pin in the 100-pin package. table 5.41 electrical ch aracteristics (1/3) (v cc = 3.0 to 3.6 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v oh high level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0top10_7, p11_0top11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (1) i oh = -1 ma v cc - 0.6 v cc v v ol low level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0top10_7, p11_0top11_4, p12_0 to p12_7, p13_0 to p13_7, p14_3 to p14_6, p15_0 to p15_7 (1) i ol = 1 ma 0.5 v
rej03b0254-0101 rev.1.01 mar 11, 2010 page 92 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v notes: 1. pins int6 to int8 are available in the 144-pin package only. 2. ports p9_0, p9_2, and p11 to p15 are available in the 144-pin package only. port p9_1 is designated as input pin in the 100-pin package. table 5.42 electrical ch aracteristics (2/3) (v cc = 3.0 to 3.6 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v t+ - v t- hysteresis hold , rdy , nmi , int0 to int8 , ki0 to ki3 , ta0in to ta4in, ta0out to ta4out, tb0in to tb5in, cts0 to cts8 , clk0 to clk8, rxd0 to rxd8, scl0 to scl6, sda0 to sda6, ss0 to ss6 , srxd0tosrxd6, adtrg , iio0_0 to iio0_7, iio1_0 to iio1_7, ud0a, ud0b, ud1a, ud1b, isclk2, isrxd2, iein, can0in, can0wu (1) 0.2 1.0 v reset 0.2 1.8 v i ih high level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_1, p14_3 to p14_6, p15_0 to p15_7 (2) v i = 3.3 v 4.0 a i il low level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_1, p14_3 to p14_6, p15_0 to p15_7 (2) v i = 0 v -4.0 a r pullup pull-up resistor p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p5_0 to p5_3, p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_1, p14_3 to p14_6, p15_0 to p15_7 (2) v i = 0 v 50 100 500 k r f xin feedback resistor xin 3m r f xcin feedback resistor xcin 25 m
rej03b0254-0101 rev.1.01 mar 11, 2010 page 93 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v table 5.43 electrical characteristics (3/3) (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characte ristic measurement condition value unit min. typ. max. i cc power supply current in single-chip mode, output pins are left open and others are connected to v ss xin-xout drive power: low xcin-xcout drive power: low f (cpu) =50mhz, f (bclk) =25mhz, f (xin) =8mhz, active: xin, pll, stopped: xcin, oco 32 45 ma f (cpu) = f so(pll) /24 mhz, active: pll (self-oscillation), stopped: xin, xcin, oco 9ma f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco 670 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown 180 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown 190 a f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) = 8 mhz, active: xin, stopped: pll, xcin, oco, t a = 25c, wait mode 500 900 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown, t a = 25c, wait mode 8 140 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown, t a = 25c, wait mode 10 150 a stopped: all clocks, main regulator: shutdown, t a = 25c 570a
rej03b0254-0101 rev.1.01 mar 11, 2010 page 94 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v note: 1. pins an15_0 to an15_7 are available in the 144-pin package only. table 5.44 a/d conversion characteristics (v cc =av cc =v ref =3.0to3.6v, v ss =av ss =0v, t a =t opr , and f (bclk) = 25 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution v ref = v cc 10 bits ? absolute error v ref = v cc = 3.3 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, an15_0 to an15_7, anex0, anex1 (1) 5 lsb external op-amp connection mode 7 lsb inl integral non-linearity error v ref = v cc = 3.3 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, an15_0 to an15_7, anex0, anex1 (1) 5 lsb external op-amp connection mode 7 lsb dnl differential non- linearity error v ref = v cc = 3.3 v 1 lsb ?offset error 3 lsb ? gain error 3 lsb r ladder resistor ladder v ref = v cc 420k t conv conversion time (10 bits) ad = 10 mhz, with sample and hold function 3.3 s t conv conversion time (8 bits) ad = 10 mhz, with sample and hold function 2.8 s t samp sampling time ad = 10 mhz 0.3 s v ia analog input voltage 0 v ref v ad operating clock frequency without sample and hold function 0.25 10 mhz with sample and hold function 1 10 mhz
rej03b0254-0101 rev.1.01 mar 11, 2010 page 95 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v note: 1. one d/a converter is used. the dai register (i = 0, 1) of the other unused converter is set to 00h. the resistor ladder for a/d converter is not considered. even when the vcut bit in the ad0con1 register is set to 0 (v ref disconnected), i vref is supplied. table 5.45 d/a conversion characteristics (v cc =av cc =v ref =3.0to3.6v, v ss =av ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution 8bits ? absolute precision 1.0 % t s settling time 3s r o output resistance 41020k i vref reference input current (1) 1.0 ma
rej03b0254-0101 rev.1.01 mar 11, 2010 page 96 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.46 external clock input symbol characteristic value unit min. max. t c (x) external clock input period 62.5 250 ns t w(xh) external clock input high level pulse width 25 ns t w(xl) external clock input low level pulse width 25 ns t r(x) external clock input rise time 5ns t f (x) external clock input fall time 5ns t w / t c external clock input duty 40 60 % table 5.47 external bus timing symbol characteristic value unit min. max. t su(d-r) data setup time for read 40 ns t h(r-d) data hold time after read 0ns t dis(r-d) data disable time after read 0.5 t c(base) + 10 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 97 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.48 timer a input (counti ng input in event counter mode) symbol characteristic value unit min. max. t c(ta) taiin input clock period 200 ns t w(tah) taiin input high level pulse width 80 ns t w(tal) taiin input low level pulse width 80 ns table 5.49 timer a input (gating input in timer mode) symbol characteristic value unit min. max. t c(ta) taiin input clock period 400 ns t w(tah) taiin input high level pulse width 180 ns t w(tal) taiin input low level pulse width 180 ns table 5.50 timer a input (external trigger input in one-shot timer mode) symbol characteristic value unit min. max. t c(ta) taiin input clock period 200 ns t w(tah) taiin input high level pulse width 80 ns t w(tal) taiin input low level pulse width 80 ns table 5.51 timer a input (external trigge r input in pulse-width modulation mode) symbol characteristic value unit min. max. t w(tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.52 timer a input (increment/decrement count switching input in event counter mode) symbol characteristic value unit min. max. t c(up) taiout input clock period 2000 ns t w(uph) taiout input high level pulse width 1000 ns t w(upl) taiout input low level pulse width 1000 ns t su(up-tin) taiout input setup time 400 ns t h(tin-up) taiout input hold time 400 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 98 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.53 timer b input (counti ng input in event counter mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock period (one edge counting) 200 ns t w(tbh) tbiin input high level pulse width (one edge counting) 80 ns t w(tbl) tbiin input low level pulse width (one edge counting) 80 ns t c(tb) tbiin input clock period (both edges counting) 200 ns t w(tbh) tbiin input high level pulse width (both edges counting) 80 ns t w(tbl) tbiin input low level pulse width (both edges counting) 80 ns table 5.54 timer b input (pulse period measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock period 400 ns t w(tbh) tbiin input high level pulse width 180 ns t w(tbl) tbiin input low level pulse width 180 ns table 5.55 timer b input (pulse-width measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock period 400 ns t w(tbh) tbiin input high level pulse width 180 ns t w(tbl) tbiin input low level pulse width 180 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 99 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.56 serial interface symbol characteristic value unit min. max. t c(ck) clki input clock period 200 ns t w(ckh) clki input high level pulse width 80 ns t w(ckl) clki input low level pulse width 80 ns t su(d-c) rxdi input setup time 80 ns t h(c-d) rxdi input hold time 90 ns table 5.57 a/d trigger input symbol characteristic value unit min. max. t w(adh) adtrg input high level pulse width hardware trigger input high level pulse width ns t w(adl) adtrg input low level pulse width hardware trigger input high level pulse width 125 ns table 5.58 external interrupt inti input symbol characteristic value unit min. max. t w(inh) inti input high level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns t w (inl) inti input low level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns table 5.59 intelligent i/o symbol characteristic value unit min. max. t c (isclk2) isclk2 input clock period 600 ns t w (isclk2h) isclk2 input high level pulse width 270 ns t w (isclk2l) isclk2 input low level pulse width 270 ns t su (rxd-isclk2) isrxd2 input setup time 150 ns t h (isclk2-rxd) isrxd2 input hold time 100 ns 3 ad --------- -
rej03b0254-0101 rev.1.01 mar 11, 2010 page 100 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated by the following formulas based on a value ssc set by bits ssc4 to ssc0 in the i2csscr register: t h(sda-scl)s = ssc 2 t c( iic) + 40 [ns] t su(scl-sda)p = (ssc 2 + 1) t c( iic) + 40 [ns] t w(sdah)p = (ssc + 1) t c( iic) + 40 [ns] table 5.60 multi-master i 2 c-bus interface symbol characteristic value unit standard-mode fast-mode min. max. min. max. t w(sclh) mscl input high level pulse width 600 600 ns t w(scll) mscl input low level pulse width 600 600 ns t r(scl) mscl input rise time 1000 300 ns t f(scl) mscl input fall time 300 300 ns t r(sda) msda input rise time 1000 300 ns t f(sda) msda input fall time 300 300 ns t h(sda-scl)s mscl high level hold time after start condition/restart condition (1) 2 t c( iic) + 40 ns t su(scl-sda)p mscl high level setup time for restart condition/stop condition (1) 2 t c( iic) + 40 ns t w(sdah)p msda high level pulse width after stop condition (1) 4 t c( iic) + 40 ns t su(sda-scl) msda input setup time 100 100 ns t h(scl-sda) msda input hold time 00ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 101 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v switching characteristics (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated by the following formulas based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative valu e, modify the value to be set. fo r the details of how to set values, refer to the hardware manual. t su(s-r) = t su(a-r) = tsu(a-r) t c(base) - 15 [ns] t w(r) = tw(r) t c(base) - 10 [ns] t su(s-w) = t su(a-w) = tsu(a-w) t c(base) - 15 [ns] t w(w) = t su(d-w) = tw(w) t c(base) - 10 [ns] table 5.61 external bus timing (separate bus) symbol characteristic measurement condition value unit min. max. t su(s-r) chip-select setup time for read refer to figure 5.6 (1) ns t h(r-s) chip-select hold time after read t c(base) - 15 ns t su(a-r) address setup time for read (1) ns t h(r-a) address hold time after read t c(base) - 15 ns t w(r) read pulse width (1) ns t su(s-w) chip-select setup time for write (1) ns t h(w-s) chip-select hold time after write 1.5 t c(base) - 15 ns t su(a-w) address setup time for write (1) ns t h(w-a) address hold time after write 1.5 t c(base) - 15 ns t w(w) write pulse width (1) ns t su(d-w) data setup time for write (1) ns t h(w-d) data hold time after write 0ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 102 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v switching characteristics (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated by the following formulas based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative valu e, modify the value to be set. fo r the details of how to set values, refer to the hardware manual. t su(s-ale) = t su(a-ale) = (tsu(a-r) - 0.5) t c(base) -15 [ns] t w(ale) = (tsu(a-r) - 0.5) t c(base) - 20 [ns] t w(r) = tw(r) t c(base) -10 [ns] t w(w) = t su(d-w) = tw(w) t c(base) -10 [ns] table 5.62 external bus timing (multiplexed bus) symbol characteristic measurement condition value unit min. max. t su(s-ale) chip-select setup time for ale refer to figure 5.6 (1) ns t h(r-s) chip-select hold time after read 1.5 t c(base) - 15 ns t su(a-ale) address setup time for ale (1) ns t h(ale-a) address hold time after ale 0.5 t c(base) - 5 ns t h(r-a) address hold time after read 1.5 t c(base) - 15 ns t d(ale-r) ale-read delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w (ale) ale pulse width (1) ns t dis(r-a) address disable time after read 8ns t w(r) read pulse width (1) ns t h(w-s) chip-select hold time after write 1.5 t c(base) - 15 ns t h(w-a) address hold time after write 1.5 t c(base) - 15 ns t d(ale-w) ale-write delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w(w) write pulse width (1) ns t su(d-w) data setup time for write (1) ns t h(w-d) data hold time after write 0.5 t c(base) ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 103 of 109 r32c/117 group 5. electrical characteristics v cc =3.3v switching characteristics (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. external circuits are required to satisfy the i 2 c-bus specification. table 5.63 serial interface symbol characteristic measurement condition value unit min. max. t d (c-q) txdi output delay time refer to figure 5.6 80 ns t h (c-q) txdi output hold time 0ns table 5.64 intelligent i/o symbol characteristic measurement condition value unit min. max. t d (isclk2-txd) istxd2 output delay time refer to figure 5.6 180 ns t h (isclk2-rxd) istxd2 output hold time 0ns table 5.65 multi-master i 2 c-bus interface (standard-mode) symbol characteristic measurement condition value unit min. max. t f(scl) mscl output fall time refer to figure 5.6 2ns t f(sda) msda output fall time 2ns t d(sda-scl)s mscl output delay time after start condition/restart condition 20 t c( iic) - 120 52 t c( iic) - 40 ns t d(scl-sda)p restart condition/stop condition output delay time after mscl becomes high 20 t c( iic) + 40 52 t c( iic) + 120 ns t d(scl-sda) msda output delay time 2 t c( iic) + 40 3 t c( iic) + 120 ns table 5.66 multi-master i 2 c-bus interface (fast-mode) symbol characteristic measurement condition value unit min. max. t f(scl) mscl output fall time refer to figure 5.6 2 (1) ns t f(sda) msda output fall time 2 (1) ns t d(sda-scl)s mscl output delay time after start condition/restart condition 10 t c( iic) - 120 26 t c( iic) - 40 ns t d(scl-sda)p restart condition/stop condition output delay time after mscl becomes high 10 t c( iic) + 40 26 t c( iic) + 120 ns t d(scl-sda) msda output delay time 2 t c( iic) + 40 3 t c( iic) + 120 ns
rej03b0254-0101 rev.1.01 mar 11, 2010 page 104 of 109 r32c/117 group 5. electrical characteristics figure 5.6 switching characteri stic measurement circuit figure 5.7 external clock input timing 30 pf pin to be measured mcu xin t w(xh) t w(xl) t r(x) t f(x) t c(x)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 105 of 109 r32c/117 group 5. electrical characteristics figure 5.8 external bus timing (separate bus) cs0 to cs3 a23 to a0, bc0 to bc3 rd d31 to d0 t h(r-d) t h(r-s) external bus timing (separate bus) read cycle t w(r) t su(s-r) t h(r-a) t su(a-r) write cycle cs0 to cs3 a23 to a0, bc0 to bc3 wr, wr0 to wr3 d31 to d0 t su(d-w) t h(w-d) t su(d-r) t h(w-s) t w(w) t su(s-w) t h(w-a) t su(a-w) measurement conditions criterion for input voltage criterion for output voltage v ih v il v oh v ol 2.5 v 0.8 v 2.0 v 0.8 v 1.5 v 0.5 v 2.4 v 0.5 v item v = 4.2 to 5.5 v cc t cr t cw v = 3.0 to 3.6 v cc
rej03b0254-0101 rev.1.01 mar 11, 2010 page 106 of 109 r32c/117 group 5. electrical characteristics figure 5.9 external bus timing (multiplexed bus) cs0 to cs3 a23 to a8, bc0 to bc3 rd d31 to d8 t h(r-d) t h(r-s) external bus timing (multiplexed bus) read timing t w(r) t su(s-ale) t h(r-a) t su(a-ale) write cycle wr, wr0 to wr3 t su(d-r) measurement conditions criterion for input voltage criterion for output voltage v ih v il v oh v ol 2.5 v 0.8 v 2.0 v 0.8 v 1.5 v 0.5 v 2.4 v 0.5 v item ale t w(ale) address t su(a-ale) a15/d15 to a0/d0, bc0/d0, bc2/d1 data t h(ale-a) t d(ale-r) t h(r-d) t su(d-r) cs0 to cs3 a23 to a8, bc0 to bc3 d31 to d8 t h(w-d) t h(w-s) t w(w) t su(s-ale) t h(w-a) t su(a-ale) t su(d-w) ale t w(ale) address t su(a-ale) a15/d15 to a0/d0, bc0/d0, bc2/d1 data t h(ale-a) t d(ale-w) t h(w-d) t su(d-w) t dis(r-a) t dis(r-d) t cr t cw v = 4.2 to 5.5 v cc v = 3.0 to 3.6 v cc
rej03b0254-0101 rev.1.01 mar 11, 2010 page 107 of 109 r32c/117 group 5. electrical characteristics figure 5.10 timing of peripheral functions taiin input taiout input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) taiin input (in falling edge counting) taiout input (input for increment/ decrement count switching) in event counter mode taiin input (in rising edge counting) t h(tin-up) tbiin input adtrg input t c(tb) t w(tbh) t w(tbl) t w(adl) clki t c(ck) t w(ckh) t w(ckl) txdi t d(c-q) t h(c-q) rxdi t su(d-c) t h(c-d) inti input t w(inl) t w(inh) nmi input 2 cpu clock cycles + 300 ns or more 2 cpu clock cycles + 300 ns or more t su(up-tin) t w(adh)
rej03b0254-0101 rev.1.01 mar 11, 2010 page 108 of 109 r32c/117 group 5. electrical characteristics figure 5.11 timing of multi-master i 2 c-bus interface mscl t h(sda-scl)s msda (input) mscl t w(sclh) t w(scll) t c(scl) t r(scl) t f(scl) msda t r(sda) t f(sda) t su(scl-sda)p t h(sda-scl)s t su(scl-sda)p msda (output) mscl t d(sda-scl)s t d(scl-sda)p t d(sda-scl)s t d(scl-sda)p mscl msda (input) t su(sda-scl) t h(scl-sda) mscl msda (output) t d(scl-sda) t w(sdah)p
rej03b0254-0101 rev.1.01 mar 11, 2010 page 109 of 109 r32c/117 group appendix 1. package dimensions appendix 1. package dimensions terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 20.1 20.0 19.9 d 20.1 20.0 19.9 e 1.4 a 2 22.2 22.0 21.8 22.2 22.0 21.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 * 1 * 2 * 3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. e terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e
a- 1 all trademarks and registered trademarks are the property of their respective owners. revision history r32c /117 group datasheet rev. date description page summary 1.00 nov 19, 2009 ? initial release 1.01 mar 11, 2010 ? second edition released ? ? added ?128 kb/20 kb? and ?256 kb/20 kb? for rom/ram capacity
notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas product s for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of t he use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application ci rcuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attentio n to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding th e suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of h uman injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion co ntrol, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a r enesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to us e renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 201 0. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .7.2

▲Up To Search▲

Price & Availability of R5F6417APFB

	To Download R5F6417APFB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .